Stacked Cache Response Pipelining for Uniform Die Latency
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Solution Overview
Problem
Conventional cache and memory stack technologies face challenges in achieving consistent response latency across multiple vertically stacked dies, leading to increased complexity and limiting the number of usable dies due to varying communication delays and response latencies.
Innovation Solution
Implement Z-dimension cache layer pipelining with an interconnect that adds clock cycles or partial cycles to communication signals, synchronizing responses across all cache layers to arrive at the cache controller during a common clock cycle, using delay logic at each layer to ensure consistent latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional pipelining is used to communicate between stacked dies, then communication between cache layers is enabled, but response latency varies significantly with physical distance from the base die, increasing controller complexity
Solution Approach 1:
The patent applies preliminary action by adding predetermined delay logic to intermediate cache layers before responses reach the base die. Each intermediate layer receives requests earlier and prepares responses with built-in delays, so all responses arrive at the base die simultaneously despite varying physical distances. This pre-synchronization eliminates the need for complex dynamic latency management at the controller.
Solution Approach 2:
The patent changes the time parameter by introducing variable delay cycles at different cache layers. The base die operates with zero delay, while intermediate layers add progressively larger delays (e.g., 1 cycle, 2 cycles, etc.) based on their position in the stack. This parameter adjustment equalizes the total response time across all layers, achieving consistent latency without complex controller intervention.
2Quantity of substance
If more stacked dies are used to increase cache capacity, then footprint is reduced and electrical performance improves, but communication delay between base die and top dies increases
Solution Approach 1:
The patent enables scaling to many stacked dies by applying preliminary delay logic at each intermediate layer. When a request reaches an intermediate cache layer, the layer prepares the response with a predetermined delay based on its position in the stack. This allows responses from dozens of stacked dies to be synchronized simultaneously at the base die, eliminating the communication delay penalty that would otherwise limit the number of usable dies.
3Speed
If direct connections are made between each stacked die and base die controller, then communication latency is reduced, but system complexity and cost increase significantly
Solution Approach 1:
The patent resolves the complexity issue by transitioning from a two-dimensional direct-connection architecture to a three-dimensional stacked architecture with pipelined communication. Instead of creating direct lateral connections between each die and the base controller (which would increase lateral wiring complexity), the patent uses vertical stacking with controlled delay logic, achieving efficient communication through the Z-dimension while maintaining simpler interconnect structures.
Data Source
AI summary
Z-dimension cache layer pipelining is described. In one or more implementations, a device includes a stacked cache having a plurality of cache layers communicatively pipelined by an interconnect that outputs responses from the cache layers for processing during a common clock cycle. In one or more implementations, a system includes a stacked cache having a plurality of cache layers, with each cache layer implemented on a different respective die within a stack of dies, a cache controller configured to send requests to the cache layers and process responses received from the cache layers, and an interconnect configured to synchronize communication between the cache controller and the stacked cache by pipelining the responses to arrive at the cache controller during a common clock cycle.