Stacked Capacitance Element Reduces Parasitic Resistance in Semiconductor Devices
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Solution Overview
Problem
The integration of memory and logic circuits on the same semiconductor substrate poses challenges due to increased parasitic resistance and capacity, which complicates manufacturing and reduces operation speed and increases power consumption, especially when a capacitance element is formed to enhance memory capacity.
Innovation Solution
A semiconductor device configuration where a multilayer wiring layer with a capacitance element embedded in a concave part and a cap layer forming the same plane as the upper surface of the coupling wiring allows for a higher capacitance element capacity by setting the height of the concave part high, reducing parasitic resistance and capacity, and enabling identical design parameters for both circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a trench type capacitance element with deep groove is formed to secure capacity, then the capacity is improved, but the manufacturing difficulty is significantly increased due to small opening diameter and deep depth
Solution Approach 1:
The patent transitions from a trench type (vertical) capacitance element to a stack type (horizontal layering) capacitance element. Instead of increasing depth in the vertical dimension, the invention uses multiple stacked layers in the horizontal dimension to achieve the required capacity, thereby avoiding the manufacturing difficulties of deep grooves while maintaining or improving capacity.
Solution Approach 2:
The patent employs a stacked structure where multiple capacitance element layers are nested vertically, with each layer consisting of electrode patterns and dielectric layers. This nesting approach allows the capacitance elements to be formed in the same layer as the contact insulating layer, reducing the need for separate deep trench formation processes.
2Quantity of substance
If the height of capacitance element is set high to gain capacity in COB structure, then the capacity is improved, but the contact height becomes high increasing parasitic resistance and capacity
Solution Approach 1:
The patent merges the formation of the capacitance element with the contact insulating layer, forming both structures simultaneously in the same layer. This integration allows the capacitance element height to be optimized for capacity without necessarily increasing contact height, as the contact structure can be separately optimized in the same layer.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the capacitance element region has optimized height and stacking for maximum capacity, while the contact region maintains appropriate height for minimal parasitic resistance. This local optimization allows both capacity and low parasitic requirements to be satisfied simultaneously.
3Adaptability or versatility
If memory circuit and logic circuit are formed over the same semiconductor substrate, then integration is increased, but design complexity is increased due to different structural requirements
Solution Approach 1:
The patent uses a universal stack type capacitance element structure that can be formed in the same layer as the contact insulating layer, providing a common manufacturing approach for both memory circuit regions and logic circuit regions. This multi-functional structure reduces design complexity by allowing the same basic structure to serve different circuit functions.
Data Source
AI summary
A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.