Stacked Capacitive Element Layout for High-Density CMOS Sensors
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Solution Overview
Problem
Existing CMOS image sensors face challenges in miniaturization and capacitance density improvement without decreasing operating voltage, leading to distorted pixel and reference signals and reduced analog-to-digital conversion accuracy.
Innovation Solution
A semiconductor device with stacked semiconductor substrates connected by metal bonding portions, where capacitive elements are connected in parallel, including N+ accumulation type MOS, MIM, and MOM capacitive elements, to increase capacitance density without reducing operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitance density is increased by reducing the film thickness of the insulating film, then the capacitance value increases, but the time dependent dielectric breakdown deteriorates and the product life is shortened
Solution Approach 1:
The patent transitions from increasing capacitance density by reducing film thickness (one-dimensional approach) to increasing capacitance by adding more capacitive elements in parallel through stacking substrates (multi-dimensional approach). This allows capacitance enhancement without compromising the integrity and thickness of individual insulating films, thereby avoiding TDDB deterioration.
Solution Approach 2:
The patent combines multiple capacitive elements from different substrates (sensor unit substrate and peripheral circuit unit substrate) into a parallel configuration. By merging the capacitance values of multiple elements (C_total = C1 + C2 + ... + Cn), the system achieves high capacitance density while maintaining adequate film thickness and reliability in each individual element.
2Quantity of substance
If the wiring space is narrowed to increase capacitance density in comb-shaped wiring capacitive elements, then the capacitance value increases, but the time dependent dielectric breakdown deteriorates and the product life is shortened
Solution Approach 1:
Instead of narrowing wiring space in a two-dimensional plane which compromises insulation reliability, the patent utilizes the third dimension by stacking substrates vertically. This allows capacitance enhancement through increased number of capacitive elements without reducing the spacing between wiring elements, thereby maintaining adequate insulation and avoiding TDDB.
3Volume of moving object
If the device is miniaturized according to scaling rules, then the device size decreases, but the analog circuit cannot be miniaturized because the operating voltage does not decrease
Solution Approach 1:
The patent merges the sensor unit and peripheral circuit unit onto a single substrate, integrating functions that were previously distributed across multiple substrates. This integration enables better space utilization and allows the analog circuit to be miniaturized along with the overall device without requiring separate substrate assemblies, thereby achieving scaling while maintaining operational requirements.
Solution Approach 2:
The patent utilizes vertical stacking arrangements and three-dimensional integration techniques to accommodate analog circuits within the miniaturized device footprint. By organizing circuit elements in vertical layers and utilizing available vertical space, the analog circuit can be included in the miniaturized device without requiring proportional increases in horizontal area, thus enabling overall device miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances capacitance density and maintains operating voltage, improving analog-to-digital conversion accuracy and enabling miniaturization of the solid-state imaging device.
Implementation Method 1
a second capacitive element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate
Data Source
AI summary
Provided is a semiconductor device capable of improving a capacitance density of a capacitive element without decreasing an operating voltage. The semiconductor device includes: a first semiconductor substrate including a first capacitive element portion including at least one capacitive element; a second semiconductor substrate stacked with respect to the first semiconductor substrate; and a second capacitive element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate. The first and second capacitive element portions are connected to each other in parallel.