3D Stacked Capacitive Units for Dense Memory Power Smoothing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated assemblies face challenges in increasing packing density and conserving semiconductor real estate while developing cost-effective capacitive units suitable for highly integrated memory configurations.
Innovation Solution
The development of three-dimensional capacitive units with vertically-stacked tiers, where each tier comprises conductive plates, insulative material, and capacitor dielectric, allowing for a compact footprint and simultaneous formation with memory components during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar capacitive units are used in integrated assemblies, then fabrication is simpler, but packing density is low and semiconductor real estate is not conserved
Solution Approach 1:
The patent transitions from planar (2D) capacitive units to three-dimensional (3D) vertically-stacked capacitive units. Multiple capacitive tiers are stacked vertically along the z-axis, utilizing the third dimension to increase packing density without expanding the lateral footprint on the semiconductor substrate. This dimensional transformation allows multiple capacitors to occupy the same planar area while maintaining electrical functionality.
Solution Approach 2:
The patent implements nested structures where conductive plates are positioned between capacitive tiers, and insulative pillars are embedded within the stack. The capacitive tiers themselves are nested vertically, with each tier containing capacitor structures that are integrated within the three-dimensional assembly. This nesting approach maximizes space utilization and increases capacitance within a compact volume.
2Area of stationary object
If capacitive units are highly integrated with memory components, then semiconductor real estate is conserved, but fabrication complexity increases
Solution Approach 1:
The patent merges the fabrication processes for capacitive units and memory components into a single integrated manufacturing sequence. The same deposition, etching, and patterning steps used to create memory structures are also employed to form the three-dimensional capacitive units. This consolidation of manufacturing steps into unified process flows reduces overall fabrication complexity despite the increased structural integration.
Solution Approach 2:
The patent employs universal fabrication techniques that serve multiple functions: the same conductive plate structures serve both as interconnect elements for memory cells and as electrode components for capacitive units. The insulative materials and structural layers are formed using identical processes regardless of whether they are part of memory or capacitive structures, enabling cost-effective highly-integrated assemblies.
3Reliability
If more capacitive units are added to stabilize power, then voltage oscillation is reduced, but device area increases
Solution Approach 1:
The patent uses vertical stacking to multiply capacitance within a compact footprint. By stacking multiple capacitive tiers vertically, the total capacitance value increases proportionally with the number of tiers, providing enhanced voltage stabilization capability without expanding the lateral device area. The capacitive unit achieves high capacitance density through three-dimensional configuration.
Solution Approach 2:
The patent employs composite structures combining conductive plates, capacitor dielectric materials, and insulative materials in a vertically-integrated assembly. This composite construction allows multiple functional elements to be packed closely together, maximizing capacitance per unit area while maintaining electrical isolation and structural integrity throughout the three-dimensional configuration.
Data Source
AI summary
Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.