Stacked Interdigitated Capacitor Layout for ADC Matching
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Solution Overview
Problem
In the design of high-accuracy analog-to-digital converters (ADCs), the accuracy and matching of capacitors are crucial, but existing MIM and MOM capacitors face challenges such as large area requirements, severe mismatch, and high costs due to additional mask layers, as well as parasitic effects that impact circuit accuracy.
Innovation Solution
The proposed solution involves a capacitor structure with a bottom conductive structure and multiple stacked middle and top conductive structures, each with interdigitated comb tooth patterns that form both sidewall and plate capacitors, reducing the matrix area and mismatch effects while minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MIM capacitor structure is used to improve accuracy, then manufacturing precision is improved, but area requirement increases and cost increases
Solution Approach 1:
The patent transitions from planar capacitor structures to a three-dimensional stacked configuration with multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) separated by dielectric layers. This vertical stacking approach increases capacitance density by utilizing the third dimension (height), thereby reducing the required footprint area while maintaining or improving capacitance accuracy through controlled layer geometries and materials.
Solution Approach 2:
The patent employs composite material structures combining multiple conductive materials (e.g., copper, aluminum, tungsten) and dielectric materials with specific properties. The conductive layers use materials optimized for different functions (low resistance, high conductivity), while dielectric layers provide controlled permittivity and mechanical stability. This composite approach enhances overall capacitor performance and accuracy without proportionally increasing area.
2Manufacturing precision
If additional mask layers are added to improve capacitor accuracy, then manufacturing precision is improved, but device complexity and production cost increase
Solution Approach 1:
The patent designs conductive layers and dielectric layers to serve multiple functions simultaneously. For example, the first conductive layer serves as both a capacitor electrode and a grounding shield, while dielectric layers provide both electrical insulation and mechanical structural support. This multi-functionality reduces the need for additional specialized mask layers and processing steps, thereby simplifying the overall manufacturing process while maintaining capacitor accuracy.
3Quantity of substance
If MOM capacitor structure with parallel fingers is used, then capacitance density is improved, but parasitic capacitance increases affecting circuit accuracy
Solution Approach 1:
The patent extracts and separates the parasitic capacitance elements from the main capacitor structure by introducing dedicated shielding layers and isolation structures. The ground shields and isolation dielectric layers are strategically positioned to capture and contain parasitic capacitance effects, preventing them from coupling into the signal path and degrading circuit accuracy, while the main capacitor achieves high capacitance density through the stacked configuration.
4Productivity
If capacitor matrix area is reduced to improve integration, then productivity is improved, but mismatch effects increase reducing accuracy
Solution Approach 1:
The patent segments the capacitor structure into multiple identical or matched unit cells stacked vertically. Each conductive layer is divided into corresponding segments (first conductive patterns, second conductive patterns, third conductive patterns) that form replicated capacitor units. This segmentation approach allows for better process control and matching across units, as each segment experiences similar manufacturing variations, thereby reducing mismatch effects even when the overall matrix area is reduced for higher integration density.
Data Source
AI summary
A capacitor can include a bottom conductive structure; at least one middle conductive structure, each middle conductive structure having a first conductive pattern and a second conductive pattern surrounding an outer side of the first conductive pattern, where the first conductive pattern and the second conductive pattern of each layer of the middle conductive structure form an interdigitated structure; and a top conductive structure having a third conductive pattern and a fourth conductive pattern arranged at an outer side of the third conductive pattern, where the third conductive pattern and the fourth conductive pattern form an interdigitated structure.