Stacked Capacitor Structure with Comb Electrodes for High Density
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Solution Overview
Problem
Conventional semiconductor capacitors face challenges in increasing capacitance per unit area as the size of semiconductor devices decreases, making it difficult to compensate for the reduced cell size with dielectric materials of high dielectric constant.
Innovation Solution
A capacitor structure is designed with vertically stacked plate electrodes, insulation layers, and comb-shaped electrodes to enhance capacitance, where plugs penetrate through insulation layers to create multiple capacitors in a layered configuration, increasing the surface area and overlap for improved capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dielectric constant of the dielectric layer is increased to improve capacitance per unit area, then the capacitance is improved, but it becomes difficult to obtain dielectric materials with sufficiently large dielectric constant to compensate for cell size reduction
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a three-dimensional stacked structure with multiple electrodes and insulation layers. By adding vertical stacking dimensions, the capacitor achieves increased capacitance per unit area without relying on high dielectric constant materials. The multiple plate electrodes (first, second, third, fourth electrodes) are vertically stacked with insulation layers between them, creating multiple capacitance contributions within the same footprint area.
Solution Approach 2:
The capacitor is divided into multiple discrete electrode and insulation layer segments. Instead of a single dielectric layer, the structure includes first and second insulation layers stacked vertically, with multiple electrodes (first, second, third, fourth electrodes) forming separate capacitive elements. This segmentation allows the total capacitance to be the sum of multiple individual capacitance contributions, achieving higher overall capacitance per unit area.
2Quantity of substance
If the thickness of the dielectric layer is reduced to improve capacitance per unit area, then the capacitance is improved, but the cell size is significantly reduced making it difficult to obtain sufficient capacitance
Solution Approach 1:
The patent compensates for reduced cell size by utilizing the vertical dimension through stacked electrodes and insulation layers. The capacitance per unit area is improved not by reducing horizontal dimensions further, but by adding vertical stacking layers (first and second insulation layers with multiple electrodes), effectively converting a two-dimensional area constraint into a three-dimensional volume solution.
Solution Approach 2:
The capacitor structure employs a nested configuration where insulation layers and electrodes are stacked one within another vertically. The first insulation layer is positioned between first and second electrodes, while the second insulation layer is positioned between third and fourth electrodes, with these layers nested vertically. This nesting allows multiple capacitive elements to occupy the same horizontal footprint, increasing capacitance density without further reducing cell size.
3Quantity of substance
If the contact area between electrodes and dielectric layer is increased to improve capacitance per unit area, then the capacitance is improved, but the cell size reduction limits the available area for increasing contact area
Solution Approach 1:
The patent resolves the area limitation by extending the capacitor structure into the vertical dimension. Multiple electrodes and insulation layers are stacked vertically, creating multiple contact interfaces (first electrode with first insulation layer, second electrode with first insulation layer, third electrode with second insulation layer, fourth electrode with second insulation layer). This vertical stacking multiplies the effective contact area without increasing the horizontal footprint, thereby improving capacitance per unit area despite cell size reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the capacitance per unit area by creating multiple capacitors through layered and overlapping structures, effectively addressing the challenge of reduced cell size in semiconductor devices.
Implementation Method 1
a first insulation layer for electrically insulating the first and second plate electrodes
Implementation Method 2
a capacitor structure holds electrons therein and emits the electrons for operating an electronic circuit
Data Source
AI summary
In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.