3D Stacked Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
Current electronic devices have low capacitance density in their capacitors due to the utilization of interdigitated electrodes at the same layer, resulting in limited thickness direction space and low capacitance values.
Innovation Solution
The capacitor design includes planar electrodes stacked with vias, columnar electrodes, and dielectric layers, allowing for parallel and series connections to increase capacitance density by utilizing three-dimensional space and simplifying manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If interdigitated electrodes are disposed at the same layer, then the manufacturing process is simple, but the capacitance density is low
Solution Approach 1:
The patent transitions from planar (2D) interdigitated electrodes to a three-dimensional stacked structure with planar electrodes at different heights connected by columnar electrodes. This vertical stacking in the thickness direction enables multiple capacitor units to occupy the same footprint area, significantly increasing capacitance density while maintaining manufacturing feasibility through standardized via and electrode formation processes
2Device complexity
If the capacitor structure is simplified to use interdigitated electrodes at the same layer, then the device complexity is reduced, but the capacitance value is limited
Solution Approach 1:
The capacitor is segmented into multiple discrete capacitor units, each comprising a planar electrode, columnar electrode, and dielectric layer. These units are stacked vertically and connected through conductive vias, allowing the total capacitance to be the sum of individual unit capacitances. This segmentation enables scalable capacitance accumulation without proportionally increasing device footprint
Solution Approach 2:
The patent implements a nested structure where columnar electrodes are positioned within vias of planar electrodes, and multiple capacitor units are stacked within the same planar footprint. The dielectric layers are nested between conductive elements, maximizing space utilization. This nested arrangement achieves high capacitance density by efficiently packing electrical components in three-dimensional space
3Quantity of substance
If three-dimensional space is utilized with stacked planar electrodes and columnar electrodes, then capacitance density increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent merges the formation of columnar electrodes and dielectric layers into a single integrated structure within the vias. The columnar electrode and dielectric layer are formed together in the same via hole, reducing the number of separate alignment steps. This merging approach relaxes cumulative alignment tolerances while achieving the desired three-dimensional capacitor structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves higher capacitance density and improved voltage withstand capability while reducing the risk of faults, with enhanced reliability and simplified manufacturing.
Implementation Method 1
The second dielectric layer surrounds a side surface of the columnar electrode, at least a part of the columnar electrode is located in the first via of the at least two planar electrodes, and at least a part of the second dielectric layer is also located in the first via of the at least two planar electrodes
Data Source
Figure 1~2a
Figure 2b~3
Figure 4a~4b
AI summary
This application provides a capacitor, a memory array, a memory, and an electronic device. The capacitor includes at least two planar electrodes that are spaced apart and stacked, where each planar electrode is provided with a first via; a first dielectric layer, where the first dielectric layer is located between the two adjacent planar electrodes; a columnar electrode, where at least a part of the columnar electrode is located in the first vias of the at least two planar electrodes; a second dielectric layer, where at least a part of the second dielectric layer is located in the first vias of the at least two planar electrodes, and the second dielectric layer surrounds a side surface of the columnar electrode; and a first plate and a second plate, where the first plate is connected to at least one first planar electrode in the at least two planar electrodes, and the second plate is connected to at least one second planar electrode in the at least two planar electrodes; or the first plate is connected to at least one first columnar electrode, and the second plate is connected to at least one second columnar electrode. Capacitance density of the capacitor can be improved according to this application.