Vertically Stacked Capacitor Layers for Area-Constrained Trimming
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Solution Overview
Problem
Conventional capacitance trimming circuits in semiconductor devices require additional mask processes and increased chip size due to the use of metal-insulator-metal (MIM) or polysilicon-insulator-polysilicon (PIP) capacitors, leading to complexity and area expansion.
Innovation Solution
A capacitance trimming circuit that utilizes vertically stacked capacitor layers with fuses to select desired capacitance, allowing for area reduction and simplified trimming operations through electrical die sorting and packaging, where fuses are used to control capacitance by cutting specific layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MIM or PIP capacitors are used in the capacitor array unit, then capacitance matching can be achieved, but the chip size increases and additional mask processes are required
Solution Approach 1:
The patent transitions from planar capacitor arrangement to vertically stacked capacitor layers, utilizing the third dimension (height) to stack multiple capacitor layers above each other. This dimensional change allows multiple capacitors to occupy a smaller footprint area on the chip while maintaining the required capacitance values, thereby reducing chip size without compromising capacitance matching capability
Solution Approach 2:
The patent employs a single capacitor structure design that serves multiple functions: it provides capacitance matching, enables trimming through fuse cutting, and reduces chip area. The vertically stacked capacitor layers with selective fuse cutting mechanisms allow the same structural unit to achieve both precision capacitance control and space efficiency
2Manufacturing precision
If MIM or PIP capacitors are used in the capacitor array unit, then capacitance matching can be achieved, but the fabrication process becomes more complicated
Solution Approach 1:
The patent merges the capacitor formation process with the standard semiconductor fabrication process by forming capacitor electrodes and insulating layers using the same deposition and patterning steps already required for other device components. This integration eliminates the need for separate additional mask processes that would be required for MIM or PIP capacitor fabrication, thereby simplifying the overall fabrication process while maintaining capacitance matching capability
Solution Approach 2:
The patent segments the capacitor array into multiple independent capacitor layers that can be formed using standard fabrication steps, with each layer being controllable through individual fuse cutting. This segmentation allows for simplified fabrication where each layer can be processed independently using conventional techniques, avoiding the complexity of forming specialized MIM or PIP structures
3Adaptability or versatility
If switches are arranged in an array to select capacitors, then capacitance trimming can be performed, but the area of the capacitance trimming circuit increases
Solution Approach 1:
The patent replaces the planar array of switches with a vertical stacking arrangement where capacitor layers are stacked above each other and selected by cutting fuses that connect specific layers to the circuit. This dimensional change from 2D switch array to 3D stacked structure with fuse selection significantly reduces the area required for the capacitance trimming circuit while maintaining the ability to select different capacitance values
Data Source
AI summary
A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.