Stacked Folded Capacitor Gates for Dense Low-Power Non-Volatile Memory
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Solution Overview
Problem
Conventional non-volatile memories, such as MRAM and flash memories, are not suitable for low-power and compact computing devices due to high write energy, low density, and high power consumption, and traditional ferroelectric memories suffer from charge degradation and disturbance issues.
Innovation Solution
The use of stacked and folded capacitor configurations in memory bit-cells, combined with endurance mechanisms like wear leveling, random swap injection, and error correction, to mitigate charge disturbance and improve memory endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memories (MRAM, flash) are used, then non-volatile storage is achieved, but power consumption and write energy are high
Solution Approach 1:
The patent segments the capacitor structure into multiple stacked capacitors (first capacitor and second capacitor) sharing a common bottom electrode. This segmentation allows the memory cell to achieve non-volatile storage functionality while reducing the area occupied by each individual capacitor, thereby lowering overall power consumption and enabling compact designs suitable for low-power devices.
Solution Approach 2:
The patent transitions from a planar capacitor arrangement to a three-dimensional stacked configuration. By stacking capacitors vertically and sharing common electrodes, the design achieves non-volatile storage in a compact footprint, reducing the area per memory cell and enabling higher density with lower power consumption compared to conventional planar architectures.
2Reliability
If multiple capacitors are used in memory bit-cells, then memory functionality is achieved, but area occupation increases
Solution Approach 1:
The patent merges multiple capacitors into a stacked configuration where the first capacitor and second capacitor share a common bottom electrode. This merging reduces the total area occupied by capacitors in the memory bit-cell while maintaining full memory functionality, as the shared electrode serves both capacitors simultaneously.
Solution Approach 2:
The patent implements a nested capacitor structure where capacitors are stacked vertically with shared electrodes. The first capacitor and second capacitor are nested in the vertical dimension, with the bottom electrode of the upper capacitor serving as the top electrode of the lower capacitor. This nesting achieves compact area occupation while preserving memory functionality.
3Reliability
If traditional ferroelectric memories are used, then non-volatile storage is achieved, but charge degradation and disturbance occur
Solution Approach 1:
The patent applies wear leveling mechanisms that redistribute write operations across different memory blocks before charge degradation occurs. By proactively balancing the wear across multiple blocks, the system prevents charge degradation and disturbance in any single block, maintaining charge stability and extending the lifespan of the ferroelectric memory.
Solution Approach 2:
The patent implements error correction codes (ECC) that continuously monitor and correct charge degradation and disturbance in ferroelectric memory. The ECC system provides feedback mechanisms that detect and correct bit errors caused by charge instability, thereby maintaining data integrity and charge stability over extended operation periods.
4Quantity of substance
If memory density is increased, then storage capacity is improved, but charge disturbance increases
Solution Approach 1:
The patent segments the memory into multiple blocks and implements wear leveling that distributes write operations across these blocks. This segmentation prevents charge disturbance from concentrating in any single high-density region, maintaining charge stability even as overall memory density increases through compact stacked capacitor designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, increases memory density, and enhances the reliability and endurance of non-volatile memories by minimizing charge disturbance and extending the lifespan of ferroelectric capacitors.
Implementation Method 1
an apparatus comprising memory and corresponding logic, wherein the memory comprises ferroelectric (FE) or paraelectric (PE) memory bit-cells
Implementation Method 2
the capacitors are in a stacked and folded configuration
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.