Stacked Capacitor Cell Layout for Lower ESR in Silicon Capacitors
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Solution Overview
Problem
Integrated circuits face challenges in reducing parasitic resistance in silicon capacitors due to high resistance characteristics of connecting conductors, which increases device area when more conductors are added.
Innovation Solution
A capacitor structure with a substrate, capacitor cells, first and second cell plates, and vias is designed to minimize resistance by using shorter vias connected to top cell plates, reducing the overall resistance and area while maintaining or increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of connecting conductors is increased to reduce parasitic resistance, then the parasitic resistance characteristics improve, but the device area increases
Solution Approach 1:
The patent transitions from planar conductor arrangement to three-dimensional stacked capacitor structure with vertical vias. Multiple capacitor cells are stacked in the vertical dimension, allowing multiple connection points without increasing lateral device area. The vias extend vertically through the stacked structure, enabling electrical connections in the third dimension while maintaining compact footprint.
Solution Approach 2:
Multiple capacitor cells are nested vertically in a stacked configuration, with each cell containing conductive plates and dielectric layers. The vias are nested within the stacked structure, passing through multiple capacitor cells to provide electrical connections. This nesting allows multiple conductors to be integrated within the same lateral footprint by utilizing vertical space.
2Reliability
If the number of connecting conductors is increased to reduce parasitic resistance, then the parasitic resistance characteristics improve, but the device complexity increases
Solution Approach 1:
Multiple capacitor cells are merged into a single stacked structure, sharing common vias and interconnect structures. The vias serve multiple capacitor cells simultaneously, providing electrical connections through the entire stack. This merging reduces the number of separate conductor elements needed compared to implementing multiple individual capacitors, thereby reducing overall device complexity while maintaining low parasitic resistance.
Solution Approach 2:
The vias in the stacked capacitor structure serve multiple functions: they provide electrical connections for multiple capacitor cells, act as interconnect elements between different stacking levels, and contribute to reducing parasitic resistance across the entire capacitor array. This multi-functionality reduces the need for dedicated separate conductors for each capacitor cell.
3Reliability
If shorter vias are used to reduce resistance, then the parasitic resistance decreases, but the capacitance density may be affected
Solution Approach 1:
The patent compensates for reduced via length by increasing the vertical stacking height of capacitor cells. Multiple capacitor cells are stacked in the vertical dimension, increasing the total capacitance through additive effect of individual cell capacitances. The extended vertical dimension provides additional capacitance volume to offset the reduced contribution from shorter vias.
Solution Approach 2:
The patent optimizes the dimensions and arrangement of capacitor cells within the stacked structure. By adjusting cell size, dielectric material properties, and stacking configuration, the overall capacitance density is maintained or enhanced despite the use of shorter vias. The parameters of the capacitor cells are tuned to compensate for the reduced via contribution to total capacitance.
Data Source
AI summary
A capacitor structure is provided. The capacitor structure includes a substrate, a plurality of capacitor cells, a first cell plate, a plurality of second cell plates, and a plurality of vias. The plurality of capacitor cells are formed upon the substrate. The first cell plate is disposed between the substrate and the plurality of capacitor cells, and the plurality of second cell plates are disposed on the plurality of capacitor cells respectively. The vias are disposed on the second cell plates. The plurality of capacitor cells are connected in series.