Stacked Capacitor Structure for Semiconductor Manufacturing Cost Reduction
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Solution Overview
Problem
The existing manufacturing processes for semiconductor devices are costly due to the separate processing of memory cells and logic circuits, and there is a need to increase the capacitance of capacitors to improve device performance.
Innovation Solution
A capacitor structure is formed with a first and second capacitor structure on a substrate, including electrodes and dielectric layers, with contact pads and wiring connecting them, allowing for simultaneous processing of both regions and increased capacitance through parallel electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processing is used for memory cells and logic circuits, then each region can be optimized independently, but manufacturing costs increase due to repeated unit processes
Solution Approach 1:
The patent merges the processing of memory cells and logic circuits into a unified process sequence. The same deposition, photolithography, and etching processes are used for both regions, eliminating the need for separate unit processes. This combining approach reduces manufacturing complexity and costs while maintaining the ability to optimize each region's structure independently through selective patterning and material deposition.
2Ease of manufacture
If conventional capacitor structures are used, then manufacturing is simpler, but capacitance is insufficient to improve device performance
Solution Approach 1:
The patent transitions from planar capacitor electrodes to vertically stacked three-dimensional capacitor structures. Multiple electrode layers and dielectric layers are deposited in sequence to form stacked capacitor units, significantly increasing the effective capacitance area without expanding the lateral footprint. This dimensional change enables higher capacitance values while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The patent implements nested capacitor structures where smaller capacitor units are formed within or alongside larger structural elements. The stacked capacitor units are integrated within the logic circuit regions, nesting the capacitor functionality within the existing device architecture. This nesting approach maximizes space utilization and achieves high capacitance without adding significant structural complexity.
3Ease of manufacture
If the number of unit processes is reduced, then manufacturing costs decrease, but process integration complexity increases
Solution Approach 1:
The patent designs deposition and etching processes that serve multiple functions simultaneously. For example, the same deposition process forms both logic circuit interconnect layers and capacitor electrode layers, while photolithography patterns define both transistor gates and capacitor structures. This multi-functionality reduces the total number of unit processes required while maintaining the complexity needed for advanced device performance.
Data Source
AI summary
A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode.