Stacked Capacitor Device with Shifted Electrodes
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Solution Overview
Problem
Capacitor devices require reduced terminal diameter and spacing, thickness, and manufacturing costs, with conventional trench capacitors limited by silicon substrate polishing and high depth, leading to increased thickness and expensive mask remaking for varying characteristics.
Innovation Solution
A capacitor device with multiple cells on a semiconductor substrate featuring layered electrodes and terminals, allowing for reduced thickness and cost-effective manufacturing by shifting electrode layers and using external terminals with comb or meander shapes for flexible capacitance and voltage configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trench capacitors are formed deeper in silicon substrate to increase capacity, then capacitance increases, but device thickness increases and polishing becomes more difficult
Solution Approach 1:
The invention transitions from vertical trench capacitors (depth direction) to planar stacked capacitors (layer direction). Multiple capacitor elements are stacked horizontally on the semiconductor substrate surface, converting the capacity increase strategy from vertical depth to horizontal layering, thereby reducing device thickness while maintaining or increasing total capacitance.
Solution Approach 2:
The capacitor structure is divided into multiple discrete stacked capacitor elements, each with its own electrode pairs and insulating layers. These segmented elements can be arranged in parallel to increase total capacitance without increasing individual element depth, thus avoiding the thickness problem of deep trench capacitors.
2Adaptability or versatility
If mask remaking is performed to change capacitor characteristics, then capacitance or voltage characteristics can be adjusted, but manufacturing cost increases significantly
Solution Approach 1:
The stacked capacitor structure uses a universal fabrication process that can produce multiple capacitor elements with different characteristics (capacitance, breakdown voltage) from the same base structure. By varying the number of stacked elements, their arrangement, or terminal connections, different electrical characteristics are achieved without remaking masks, making the process universally applicable to multiple product specifications.
Solution Approach 2:
The invention enables dynamic adjustment of capacitor characteristics through flexible terminal selection and connection configurations. Different terminals can be connected to different electrode pairs within the stacked structure, allowing capacitance and voltage ratings to be dynamically adjusted after fabrication without requiring new masks or process changes.
3Area of stationary object
If terminal diameter and spacing are reduced for further circuit integration, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The invention moves terminal connections from vertical through-substrate paths to horizontal surface-level connections between stacked capacitor elements. This dimensional shift allows terminals to be positioned and connected at the substrate surface using standard fine-pitch semiconductor fabrication techniques, reducing the need for high-precision deep-hole alignment while achieving compact device footprints.
Data Source
AI summary
In the present invention, lower electrodes (101, 102) are disposed at a period d1 in an X direction and at a period d2 in a Y direction. Upper electrodes (102) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the lower electrodes (101), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the lower electrodes (101). Each pair of a lower electrode (101) and an upper electrode (102), which face each other and capacitively couple with each other, form a capacitor cell (C). Cell terminals (103, 104) are disposed at the period (d1) in the X direction, disposed at the period (d2) in the Y direction, and respectively electrically connected to the lower electrodes (101) and the upper electrodes (102). The cell terminals (104) are disposed so as to be shifted by half the length of the period (d1) in the X direction with respect to the cell terminals (103), and are disposed so as to be shifted by half the length of the period (d2) in the Y direction with respect to the cell terminals (103).