Stacked Capacitor Structure for Stable Capacitance in Scaled Semiconductors

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Solution Overview

Problem

The semiconductor industry faces challenges in forming reliable semiconductor devices at smaller sizes due to increased complexity and difficulty in fabrication processes as feature sizes decrease, requiring innovative solutions to maintain device performance and reliability.

Innovation Solution

The semiconductor device structure incorporates stacked capacitor elements with capacitor dielectric layers made of different materials, such as oxide and nitride materials with varying stress levels, to compensate for temperature and voltage coefficients, ensuring consistent capacitance and reliability across different operation conditions, and the use of specific deposition processes to control grain sizes of conductive and barrier layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes are decreased to increase functional density, then productivity and cost efficiency are improved, but manufacturing complexity and fabrication difficulty increase

Engineering Contradiction:
Improveproduction efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the capacitor structure into multiple discrete layers (first capacitor dielectric layer, second capacitor dielectric layer, intermediate conductive layer, upper and lower conductive layers) that can be formed through separate fabrication steps. This segmentation allows each layer to be optimized and controlled independently, managing the complexity of forming reliable devices at smaller sizes while maintaining high functional density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different materials with different stress characteristics (oxide material with first stress, nitride material with second stress) to different locations within the capacitor structure. This local differentiation of material properties enables precise control over capacitance and breakdown voltage at specific regions, addressing reliability challenges in scaled-down devices without increasing overall processing complexity

Inventive Principle:
Principle #3Local quality

2Productivity

If feature sizes are decreased to increase functional density, then production efficiency is improved, but device reliability becomes more difficult to maintain

Engineering Contradiction:
Improveproduction efficiencyVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs a composite capacitor structure combining oxide dielectric material and nitride dielectric material, each contributing different electrical and mechanical properties. This composite approach enhances breakdown voltage and capacitance reliability in scaled devices, maintaining high reliability even as feature sizes decrease to improve production efficiency

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent controls the stress parameters of the dielectric layers (first stress in the oxide layer, second stress in the nitride layer) to optimize electrical performance. By adjusting these stress parameters, the invention achieves improved breakdown voltage and capacitance stability, ensuring device reliability in miniaturized semiconductor structures

Inventive Principle:
Principle #35Parameter changes

3Reliability

If stacked capacitor elements with different dielectric materials are used to compensate temperature and voltage coefficients, then capacitance consistency is improved, but device complexity increases

Engineering Contradiction:
Improvecapacitance consistencyVSAvoidcapacitor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The intermediate conductive layer serves multiple functions: it acts as an electrode for the first capacitor, provides a bonding interface between the two capacitor dielectric layers, and enables electrical connection between the upper and lower conductive layers. This multi-functionality reduces the need for additional separate components, maintaining capacitance consistency without proportionally increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the formation of two separate capacitors into a single stacked structure where the first capacitor dielectric layer, second capacitor dielectric layer, and intermediate conductive layer are integrated. This combined structure achieves temperature and voltage coefficient compensation while minimizing the increase in device complexity through efficient space utilization

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for improved capacitance and breakdown voltage while maintaining reliability and performance even under changing operation conditions, effectively addressing the challenges of scaling down semiconductor device fabrication.

Implementation Method 1

capacitor dielectric layers made of different materials, such as oxide and nitride materials with varying stress levels, to compensate for temperature and voltage coefficients

Methodology Applied
Scientific EffectTemperature coefficient compensation:

Implementation Method 2

capacitor dielectric layers made of different materials, such as oxide and nitride materials with varying stress levels, to compensate for temperature and voltage coefficients

Methodology Applied
Scientific EffectVoltage coefficient compensation:

Implementation Method 3

the use of specific deposition processes to control grain sizes of conductive and barrier layers

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS20240355817A1Structure and formation method of semiconductor device with capacitors
Publication Date: 2024.10.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240355817A1 patent drawing
  • US20240355817A1 patent drawing
  • US20240355817A1 patent drawing

AI summary

The present disclosure relates to a semiconductor structure. The semiconductor structure includes a first electrode over a substrate. A first capacitor dielectric layer is over an upper surface of the first electrode. The upper surface of the first electrode laterally extends to opposing outermost sidewalls of the first capacitor dielectric layer. A second electrode is over the first capacitor dielectric layer. The upper surface of the first electrode extends past opposing sides of the second electrode. A second capacitor dielectric layer is over the second electrode. A third electrode has a lower surface directly over an upper surface of the second capacitor dielectric layer and completely confined over the second electrode.