Stacked Capacitor Structure With Supported High-Aspect Electrodes
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Solution Overview
Problem
The aspect ratio of freestanding bottom electrodes in memory devices, such as DRAM, is limited due to manufacturing processes, leading to potential damage and reduced capacitance.
Innovation Solution
A method for manufacturing stacked capacitor structures involves sequential deposition of dielectric and etch stop layers, followed by patterning and planarization techniques to form supported bottom electrodes with increased aspect ratios, preventing damage during subsequent processes and enhancing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size of a memory cell is reduced to increase storage capacity, then the storage density is improved, but the aspect ratio of the freestanding bottom electrode is dramatically increased making it prone to damage
Solution Approach 1:
The patent introduces a support electrode structure that segments the capacitor formation process into distinct stages: first forming a bottom electrode with initial support, then adding a top electrode. This segmentation prevents the freestanding bottom electrode from being damaged during subsequent manufacturing processes by providing structural support at different stages of capacitor formation.
Solution Approach 2:
The patent uses an intermediary support structure (the support electrode and associated dielectric layers) that mediates between the miniaturized memory cell requirements and the mechanical stability needs of the bottom electrode. This intermediary structure provides the necessary support during manufacturing while allowing the final capacitor to achieve the required high aspect ratio for increased storage capacity.
2Quantity of substance
If the aspect ratio of the bottom electrode is increased to enhance capacitance, then the capacitance is improved, but the electrode becomes prone to damage during subsequent manufacturing processes
Solution Approach 1:
The patent applies preliminary action by forming the support electrode structure and dielectric layers before completing the capacitor formation process. This preliminary structural support is established to prevent bottom electrode damage during subsequent manufacturing steps, allowing the high aspect ratio capacitor to be formed without compromising electrode integrity.
Solution Approach 2:
The patent implements beforehand cushioning by introducing support structures (support electrode and dielectric layers) that cushion and protect the bottom electrode from mechanical damage during subsequent manufacturing processes. This protective structure is in place before the potential damage can occur, enabling the production of high aspect ratio capacitors with aspect ratios up to 12:1.
3Quantity of substance
If the aspect ratio of the capacitor is increased to enhance capacitance, then the capacitance is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated structures: the support electrode serves both as a structural support element and as part of the electrical connection path. The dielectric layers serve both as electrical insulation and as structural support. This merging reduces the number of separate components and simplifies the manufacturing process while still achieving the required high aspect ratio capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for increased aspect ratios of capacitor segments up to 12, thereby enhancing the capacitance of memory devices without electrode damage, improving manufacturing efficiency.
Implementation Method 1
sequential deposition of dielectric and etch stop layers
Data Source
AI summary
A method for manufacturing a stacked capacitor structure includes: forming a first patterned structure over a substrate; forming a first bottom electrode over the first patterned structure; depositing a first dielectric film over the first bottom electrode; depositing a first top electrode layer over the first dielectric film; forming a first vertical interconnect structure; forming a second patterned structure over the first top electrode layer; forming a second bottom electrode over the second patterned structure and electrically connected to the first bottom electrode through the first vertical interconnect structure; depositing a second dielectric film over the second bottom electrode; depositing a second top electrode layer over the second dielectric film; and forming a second vertical interconnect structure extending from the first top electrode layer. The second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.