Stacked Capacitor Vertical Integration for IC Footprint Reduction
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Solution Overview
Problem
Integrated circuits face challenges in achieving high capacitance density, reducing footprint area, and minimizing voltage coefficient and mismatch in capacitors, while maintaining manufacturing reliability.
Innovation Solution
A stacked capacitor arrangement is fabricated within an integrated circuit, where two capacitors are connected in parallel, with each capacitor comprising multiple layers of conductive and dielectric materials, allowing for a smaller footprint and higher capacitance density by stacking them vertically, which also reduces voltage coefficient mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single large capacitor is used to achieve high capacitance, then the capacitance value is sufficient, but the footprint area occupied is large
Solution Approach 1:
The patent transitions from a planar single-layer capacitor layout to a three-dimensional stacked configuration with multiple capacitors arranged vertically across different metal layers. This dimensional change allows the total capacitance to be distributed across multiple smaller capacitor units in the vertical dimension, thereby achieving the required capacitance value while reducing the horizontal footprint area on the substrate.
Solution Approach 2:
The total capacitance requirement is segmented into multiple smaller capacitor units (first capacitor, second capacitor, third capacitor) that are distributed across different metal layers. Each capacitor unit contributes a portion of the total capacitance, and their combined effect achieves the desired capacitance value while each individual unit occupies a smaller area than a single large capacitor would require.
2Area of stationary object
If multiple capacitors are stacked vertically to reduce footprint area, then the area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes of multiple capacitors into a unified manufacturing flow. All capacitor structures are formed simultaneously using the same sequence of deposition and etching steps applied across multiple metal layers, rather than fabricating each capacitor separately. This merging of processes reduces the overall manufacturing complexity despite the increased vertical stacking.
Solution Approach 2:
The manufacturing process is designed with universal steps that serve multiple functions: the same dielectric layer deposition and etching procedures create capacitor structures across different metal layers, and the same process sequence forms both the capacitor electrodes and the interconnect structures. This multi-functionality reduces the number of unique process steps required.
3Area of stationary object
If capacitor width is reduced to decrease footprint, then the area is smaller, but the voltage coefficient and mismatch increase
Solution Approach 1:
The total capacitance is divided into multiple smaller capacitor units distributed across different metal layers. By segmenting the capacitance into multiple units rather than using a single small capacitor, the patent maintains better voltage coefficient characteristics and reduces mismatch, as the statistical variation and voltage coefficient effects are averaged across multiple units.
Solution Approach 2:
The patent moves the capacitor structures into the vertical dimension by stacking them across multiple metal layers. This allows each capacitor to have a smaller planar width while the total capacitance is achieved through the cumulative effect of multiple layers, thereby reducing footprint area without compromising the voltage coefficient and mismatch characteristics that would result from simply reducing the width of a single capacitor.
Data Source
AI summary
An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.