Vertically Stacked Embeddable Capacitors for High-Density IC Integration
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Solution Overview
Problem
Current on-chip capacitor techniques in ICs cannot achieve high enough capacitance densities required for modern electronic devices, particularly at frequencies above 5 GHz, leading to the need for discrete capacitors that occupy valuable planar area, hindering the miniaturization of electronic products.
Innovation Solution
The integration of discrete embeddable capacitors using vertical stacking on IC chips, allowing for higher capacitance densities (up to 1 μF) without increasing the 2D footprint, through methods like hybrid bonding and thermo-compression bonding, and utilizing through-silicon vias for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If discrete capacitors are mounted on module substrate or PCB, then high capacitance values can be achieved, but planar area consumption increases
Solution Approach 1:
The patent transitions from two-dimensional planar mounting of discrete capacitors on PCB surfaces to three-dimensional integration by embedding capacitors within the IC chip structure itself. This vertical integration into the third dimension eliminates the need for separate planar mounting space while maintaining high capacitance values through stacked capacitor configurations within the chip volume.
Solution Approach 2:
The patent merges previously separate components (IC chip and discrete capacitors) into a single integrated structure. By combining the capacitor fabrication process with the IC chip manufacturing process, the capacitors become an integral part of the chip, eliminating the need for separate mounting and reducing overall planar area consumption.
2Ease of manufacture
If on-chip capacitors are fabricated using MIM, MOM, or MOS processes, then integration is achieved, but capacitance density is insufficient for modern applications
Solution Approach 1:
The patent overcomes the capacitance density limitation of planar on-chip capacitors by transitioning to three-dimensional stacked capacitor structures. Multiple capacitor layers are vertically stacked within the chip, achieving capacitance densities measured in micro-Farads per square millimeter compared to the pico-Farads per square millimeter of traditional planar capacitors.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor elements are stacked one within another in the vertical dimension. This nested configuration allows multiple capacitance values to be integrated in a compact volume, achieving high capacitance density while maintaining compatibility with standard IC fabrication processes.
3Quantity of substance
If discrete capacitors are used to achieve high capacitance densities, then capacitance requirements are met, but device size increases
Solution Approach 1:
The patent resolves the size-capacitance tradeoff by moving from two-dimensional planar expansion to three-dimensional vertical stacking. High capacitance values are achieved through vertical integration within the chip volume rather than lateral expansion, maintaining compact device footprint while meeting high capacitance density requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significantly higher capacitance densities while reducing the planar area consumption, compatible with CMOS fabrication temperatures, and allows for the integration of larger capacitances without expanding the IC chip's footprint, addressing the limitations of existing on-chip capacitor technologies.
Implementation Method 1
The integration of discrete embeddable capacitors using vertical stacking on IC chips, allowing for higher capacitance densities (up to 1 μF) without increasing the 2D footprint, through methods like hybrid bonding and thermo-compression bonding
Implementation Method 2
The integration of discrete embeddable capacitors using vertical stacking on IC chips, allowing for higher capacitance densities (up to 1 μF) without increasing the 2D footprint, through methods like hybrid bonding and thermo-compression bonding
Implementation Method 3
utilizing through-silicon vias for efficient electrical connections
Data Source
AI summary
Single-chip solutions and related methods that result in much higher capacitance densities than is achievable with current on-chip solutions and which reduce consumption of planar area of a mounting structure. Embodiments of the present invention use vertical stacking to affix one or more discrete embeddable capacitors to an IC chip superstructure or base structure, and either sequentially or concurrently form electrical connections between the discrete embeddable capacitors and the IC chip. The inventive processes are compatible with CMOS fabrication temperatures for the IC chip while allowing use of capacitors that are fabricated using other processes that may involve much higher temperatures. The inventive processes allow connection of relatively large capacitances (e.g., ˜0.5 μF-1 μF) to an IC chip without increasing the 2-D footprint of the IC chip. Some embodiments include reconfigurable discrete/affixed capacitors and/or discrete/affixed capacitors with through-vias (distinct from capacitor electrode connections) for connecting circuitry.