Stacked Decoupling Capacitors for Low-Noise SERDES Circuits
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Solution Overview
Problem
High-speed SERDES devices, particularly those used in AI and ML applications, face challenges with increased susceptibility to amplitude noise and interference due to the use of PAM 4 signaling, which requires effective decoupling capacitors to manage noise and jitter in high-frequency communication channels.
Innovation Solution
A stacked chip structure is employed, where a 'capacitance' wafer with distributed capacitance units is bonded directly above a 'logic' wafer, providing decoupling capacitors with low parasitic impedance to replace traditional integrated capacitors like MiM or MOM capacitors, thereby reducing noise and jitter in SERDES circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PAM 4 signaling is used to double the bit-rate within a communication channel, then data rate is improved, but susceptibility to amplitude noise and interference increases
Solution Approach 1:
The patent transitions from planar integrated capacitors (MiM, MOM) to three-dimensional stacked capacitor structures. By stacking multiple capacitor layers vertically, the patent achieves higher decoupling capacitance density while reducing the parasitic inductance associated with horizontal trace lengths. This dimensional change directly addresses the noise susceptibility problem by providing more effective decoupling in a compact volume.
Solution Approach 2:
The patent divides the decoupling capacitance function into multiple separate capacitor layers stacked vertically, with each layer contributing to the total decoupling capability. This segmentation allows for optimized placement of decoupling capacitance closer to the SERDES circuits, reducing the loop area and parasitic inductance, thereby improving noise immunity while maintaining high data rates.
2Object-affected harmful factors
If power supply decoupling capacitors with very low parasitic impedance are used to filter supply noise, then noise filtering is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple capacitor functions into a single stacked capacitor assembly that is integrated with the logic wafer. By combining multiple capacitor layers, interconnect structures, and decoupling functions into one unified three-dimensional structure, the patent reduces the number of discrete components and simplifies the overall device architecture while achieving low parasitic impedance for effective noise filtering.
Solution Approach 2:
The stacked capacitor structure serves multiple functions simultaneously: it provides decoupling capacitance, acts as a power supply filter, and reduces parasitic inductance. The same vertical interconnect structures serve both as electrical connections and as part of the capacitor assembly, eliminating the need for separate trace routing and reducing overall device complexity.
3Ease of manufacture
If traditional integrated MiM or MOM capacitors are used in SERDES devices, then manufacturing is simplified, but adequate decoupling capacitance cannot be achieved without additional integrated capacitors
Solution Approach 1:
The patent moves from two-dimensional planar capacitor layouts to three-dimensional stacked structures. By utilizing the vertical dimension, the patent achieves much higher decoupling capacitance values without increasing the planar footprint or requiring additional discrete capacitor components. This dimensional transition maintains compatibility with standard semiconductor manufacturing processes while dramatically improving decoupling performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked chip structure effectively reduces supply voltage undershoot and improves the stability of SERDES circuits by providing adequate decoupling capacitance, allowing for higher clock frequencies and performance without the need for additional integrated capacitors.
Implementation Method 1
a stacked chip structure may comprise a first 'logic' wafer and a second 'capacitance' wafer, the capacitance wafer being provided directly above the logic wafer and attached to it
Data Source
AI summary
A computer structure comprises a first silicon substrate in which is formed computer circuitry and analogue circuitry for supporting communications. A second silicon substrate comprises a plurality of distributed capacitance units, and is connected to the first substrate via a set of connectors arranged extending depth-wise of the structure. The second substrate has an outer surface on which are arranged a supply voltage connector terminal and a ground connector terminal for connecting the computer structure to a supply voltage for the analogue circuitry and to ground respectively. One or more of the distributed capacitance units of the second silicon substrate is connected between the supply voltage connector and the ground connector terminal via one or more of the set of connectors to provide a decoupling capacitor for the analogue circuitry.