Stacked Cascode Circuit for DPA 6 dB Back-Off Efficiency
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Solution Overview
Problem
Digital power amplifiers (DPAs) exhibit reduced efficiency at the 6 dB back-off operating point, limiting their power efficiency and battery life in applications like mm-wave beamforming systems, where existing back-off enhancement methods provide low effectiveness.
Innovation Solution
The proposed solution involves a circuit design with stacked cascode circuits and parallel signal paths, utilizing transistors to create low impedance connections in the off-state, reducing electrical impedance by 50% and improving power efficiency by enabling high-frequency bypass and low impedance at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional digital power amplifier circuit design is used, then device complexity is reduced, but power efficiency deteriorates at 6 dB back-off operating point
Solution Approach 1:
The circuit is divided into two separate cascode circuits (first and second) with distinct signal paths, allowing independent optimization of each path's impedance characteristics. This segmentation enables the first signal path to provide low impedance at fundamental frequencies while the second signal path provides low impedance at harmonics, resolving the back-off efficiency problem without excessive complexity
Solution Approach 2:
The invention extends the impedance optimization from a single-dimensional approach to a multi-dimensional approach by creating parallel signal paths that operate at different frequency dimensions. The first cascode circuit handles fundamental frequency components while the second cascode circuit handles harmonic components, achieving comprehensive impedance control across multiple frequency dimensions simultaneously
2Use of energy by moving object
If back-off enhancement methods are applied, then power efficiency is improved, but effectiveness remains low
Solution Approach 1:
Each cascode circuit is designed with specific local impedance characteristics tailored to its function. The first cascode circuit is optimized for fundamental frequency low impedance, while the second cascode circuit is optimized for harmonic frequency low impedance. This local quality differentiation ensures that each part of the system contributes effectively to overall back-off enhancement, achieving high effectiveness rather than generic low effectiveness
Solution Approach 2:
The two cascode circuits act as intermediary elements that mediate between the power amplifier's output and the load. By introducing these intermediary circuits with specifically designed impedance characteristics, the system achieves effective back-off enhancement through controlled impedance transformation and matching at different frequency components
3Use of energy by moving object
If electrical impedance is reduced by 50%, then power efficiency is improved, but circuit complexity increases
Solution Approach 1:
The invention merges two cascode circuits in parallel, where each circuit contributes to impedance reduction at different frequency components. The combined effect of both circuits achieves the 50% impedance reduction target while distributing the complexity across two simpler, modular units rather than one complex unit, making the overall system more manageable and implementable
Data Source
AI summary
A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.