Dynamic Stacked Cascode DAC for Parasitic Capacitance Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current-steering DACs suffer from performance degradation due to dependency on load impedance and parasitic capacitance distortions caused by data-dependent charging and discharging at nodes between stacked transistors and current-steering switches.
Innovation Solution
Implementing a dynamic stacked transistor architecture in DACs where stacked transistors are turned off when corresponding current-steering switches are opened, preventing parasitic capacitance discharge and reducing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked transistors are used in current-steering DACs, then load impedance dependency is reduced, but parasitic capacitance distortions increase due to data-dependent charging and discharging
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by adding complementary stacked transistors that are specifically designed to counteract the data-dependent charging and discharging of parasitic capacitance at the cascode nodes. These additional transistors isolate the parasitic capacitance from affecting the output signal.
Solution Approach 2:
The patent uses a composite transistor architecture where regular stacked transistors for load isolation are combined with complementary stacked transistors for parasitic capacitance compensation. This composite structure achieves both load impedance independence and parasitic capacitance distortion reduction simultaneously.
2Reliability
If stacked transistors are used to reduce load impedance dependency, then DAC performance improves, but leakage current increases
Solution Approach 1:
The patent implements dynamic control of the stacked transistor gates using complementary signaling. The stacked transistors are turned on or off based on the data signal, allowing the circuit to adapt its impedance and leakage characteristics dynamically rather than maintaining a fixed state, thereby reducing overall leakage while maintaining performance.
3Object-generated harmful factors
If dynamic stacked transistor architecture is implemented, then parasitic capacitance effects are reduced, but device complexity increases
Solution Approach 1:
The complementary stacked transistors serve multiple functions simultaneously: they compensate for parasitic capacitance distortions, provide additional load isolation, and enable dynamic control of the cascode nodes. This multi-functionality reduces the need for separate compensation circuits, thereby limiting the increase in overall device complexity.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.