Stacked GaN HEMT-MOSFET Cascode Package With Top-Side Vias
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving a normally-off operation mode for Wide Band Gap (WBG) devices like SiC JFET and GaN HEMT, particularly in stack-die configurations, due to issues such as known good die (KGD) and space constraints, which affect performance and size reduction.
Innovation Solution
A semiconductor device comprising a GaN HEMT die and a MOSFET die in a cascode configuration, encapsulated with metalized vias for terminal distribution, and a manufacturing method involving die attachment, encapsulation, via drilling, metallization, and sintering to create terminals, enabling KGD solution and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a stack-die configuration is used for WBG devices, then the drain-source on resistance is improved and space is reduced, but the known good die issue and manufacturing complexity worsen
Solution Approach 1:
The device is divided into two separate dies (WBG die and silicon die) that are stacked vertically. Each die can be manufactured and tested independently, allowing known good die to be selected and combined, thus improving manufacturing precision while managing complexity through modular assembly
Solution Approach 2:
One die (silicon die) is placed directly on top of another die (WBG die) in a vertical stack configuration. This nesting approach reduces the overall footprint and improves electrical performance by minimizing parasitic inductance, while allowing independent processing of each die layer
2Adaptability or versatility
If multiple bare die are used in a power module, then flexible layout is achieved, but the footprint area increases
Solution Approach 1:
The layout transitions from a two-dimensional side-by-side arrangement to a three-dimensional vertical stack. This dimensional change allows the device to maintain layout flexibility while significantly reducing the footprint area by utilizing the vertical dimension for interconnections
3Ease of manufacture
If a side-by-side configuration is used for cascode, then manufacturing is simplified, but the footprint area increases and performance is reduced
Solution Approach 1:
The configuration transitions from horizontal side-by-side placement to vertical stacking. This dimensional change reduces the footprint area by approximately 4-5 times while maintaining manufacturing simplicity through standardized die attach processes and automated assembly techniques
4Temperature
If direct bonded copper substrate is used, then thermal performance is improved, but the device complexity and cost increase
Solution Approach 1:
The silicon die itself serves as the thermal management component with its inherent thermal conductivity and heat spreading capability. The device structure utilizes the natural thermal properties of the silicon substrate to conduct heat away from the junction, eliminating the need for additional complex thermal management layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a near chip scale package with improved electrical and thermal performance, supports final testing, and allows flexible substrate layout, reducing footprint from 12×12 (CCPAK) to 5×6, and enables easy manufacturing and assembly, suitable for power modules.
Implementation Method 1
The second die is attached using a die attach adhesive or solder
Implementation Method 2
an encapsulant deposited on the top of the semiconductor device, wherein the encapsulant is covering the first die and the second die
Implementation Method 3
Metalized vias are created within the encapsulant, wherein the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device
Data Source
AI summary
A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device.