Stacked Cascode VGA for Wideband Gain Range and Phase Control
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Solution Overview
Problem
Conventional variable gain amplifiers (VGAs) in phased radar arrays face challenges in achieving high gain range with fine control and operating at higher frequencies without increasing circuit footprint or requiring multiple stages, which leads to signal compression and phase shift issues.
Innovation Solution
A single-stage VGA circuit with a two-stage, stacked cascode configuration using NPN transistor pairs for fine and coarse gain control, where each NPN transistor pair has one conducting transistor at a time, steers RF input signal current either to the output or to the voltage rail, utilizing metal-insulator-metal (MIM) capacitors for shielding and bias resistors for control, allowing for high-frequency operation with improved gain range and phase variation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple VGA circuits are arranged in stages to increase gain range, then gain range is improved, but circuit footprint and power requirements increase
Solution Approach 1:
The patent implements a two-stage stacked cascode configuration where transistors are nested vertically in three-dimensional space. The first cascode stage (Q1-Q2) and second cascode stage (Q3-Q4) are stacked one above the other, sharing common current paths and control signals. This nesting approach achieves extended gain range equivalent to multiple horizontal stages while occupying minimal planar footprint, as the stages are integrated in the vertical dimension rather than spread out horizontally.
2Power
If multiple VGA circuits are arranged in stages to increase gain range, then gain range is improved, but power requirements increase
Solution Approach 1:
The patent merges multiple gain control functions into a unified stacked cascode structure. The first and second cascode stages share common control signals (Vctrl1, Vctrl2) and operate in series with a single differential pair (Q5-Q6). This consolidation achieves the power efficiency of a single stage while delivering the extended gain range of multiple stages, as all transistors draw from the same biased current source rather than requiring separate power supplies for each stage.
Solution Approach 2:
The control signals Vctrl1 and Vctrl2 serve multiple functions simultaneously: they control the gain of both cascode stages, regulate current distribution between parallel transistor pairs, and maintain proper biasing across the entire stacked structure. This multi-functionality eliminates the need for separate control circuits for each stage, reducing overall power consumption while achieving extended gain range.
3Power
If higher gain is realized through progressive VGA stages, then gain range is improved, but input signal compression is exacerbated
Solution Approach 1:
The patent implements dynamic gain control through the stacked cascode configuration where the effective gain is continuously adjustable via control signals Vctrl1 and Vctrl2. The first cascode stage (Q1-Q2) and second cascode stage (Q3-Q4) can be independently biased to distribute the total gain requirement, preventing any single stage from operating in deep saturation. This dynamic distribution of gain across stages reduces signal compression effects while maintaining high overall gain range.
Data Source
AI summary
A variable gain amplifier having a stacked configuration of cascode connected groups of NPN transistors is arranged in a compact schematic design. A differential radio frequency input signal is received at input nodes which is directed to a fine gain control circuit which conducts at least a portion of the received RF signal to a coarse gain control circuit that is downstream of the fine gain control circuit. The coarse gain control circuit steers current to an output node. Gain control circuits include transistor pairs. The base electrodes of each transistor pair receive inverse control signals which cause only one of the transistors in the transistor pair to conduct current. Collector electrodes of each first transistor of the pair is coupled to a downstream node in the VGA circuit, while collector electrodes of each second transistor of the pair is shunted to the voltage rail.