Stacked Memory Cell Channels With Segmented Via Routing
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and performance due to limitations in transistor structure and wiring configurations, which affect electrical characteristics and reliability.
Innovation Solution
The semiconductor memory device incorporates a novel structure with stacked cell channel patterns perpendicular to the substrate, optimized contact vias, and a stepped word line configuration, ensuring uniform heights of channel patterns and reduced contact via lengths to enhance integration and electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell channel patterns are stacked vertically to increase integration density, then device integration is improved, but contact via length increases causing electrical reliability deterioration
Solution Approach 1:
The patent transitions from planar channel patterns to vertically stacked channel patterns, utilizing the third dimension (height) to increase storage density. Multiple channel patterns are stacked in the vertical direction above the substrate, allowing more memory cells to be packed into the same footprint area while maintaining electrical connection through optimized contact via structures.
Solution Approach 2:
The contact via structure is segmented into multiple portions: a first contact via connecting the bit line to the upper wiring structure, and a second contact via connecting the upper wiring structure to the cell channel patterns. This segmentation allows optimization of each via's length and position, reducing the total effective electrical path length while maintaining vertical stacking benefits.
2Reliability
If peripheral transistor channel height is increased to improve performance, then electrical characteristics are improved, but manufacturing precision deteriorates due to height mismatch with cell channels
Solution Approach 1:
The patent applies different height characteristics to different regions: cell channel patterns maintain uniform height for manufacturing precision, while the peripheral channel pattern is positioned at a different height level (upper surface equal to or higher than cell channels). This local differentiation allows the peripheral transistor to have optimized electrical characteristics without compromising the manufacturing precision of the main memory array.
3Reliability
If contact via length is reduced to improve electrical reliability, then manufacturing complexity increases due to stepped wiring structures
Solution Approach 1:
The upper wiring structure serves multiple functions simultaneously: it acts as a connection node between the bit line and cell channel patterns through the first contact via, and as a connection node to the peripheral transistor through the second contact via. This merging of functions into a single wiring layer reduces the need for additional intermediate wiring layers, simplifying the overall manufacturing process despite the stepped configuration.
Data Source
AI summary
A semiconductor memory device includes a substrate including a cell region and a peripheral circuit region, a peripheral transistor on the peripheral circuit region and including a peripheral channel pattern, a plurality of cell channel patterns stacked on the cell region in a first direction, the first direction being perpendicular to an upper surface of the substrate, a word line on the plurality of cell channel patterns and the word line extending in a second direction, the second direction being perpendicular to the first direction, and a bit line connected to each of the plurality of cell channel patterns and the bit line extending in the first direction.