Stacked CFET Front-and-Back Interconnect Via Through-Dielectric Vias
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Solution Overview
Problem
Existing technologies face challenges in efficiently interconnecting complementary field-effect transistors (CFETs) to increase transistor density in integrated circuits, particularly in forming reliable electrical and signal connections between vertically stacked transistors.
Innovation Solution
A method involving the formation of a dielectric region, referred to as a single diffusion break (SDB) region, which is etched to create a through-via that extends from the top surface to the bottom level of the transistors, allowing for electrical and signal interconnection between the front and backside of the wafer, using a conductive material like metal to fill the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked transistors are interconnected to increase transistor density, then transistor density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements front-and-back interconnection, utilizing both the front surface and back surface of the wafer for electrical connections. This dimensional approach allows transistors to be interconnected through multiple surfaces, effectively increasing transistor density while distributing the interconnection complexity across different spatial dimensions rather than concentrating it in a single plane.
Solution Approach 2:
The interconnection structure is divided into separate front-side and back-side components. Through-holes are formed independently on each surface and then connected, allowing the complex interconnection task to be segmented into manageable stages. This reduces the overall manufacturing complexity by breaking down the monolithic interconnection problem into discrete, controllable steps.
2Reliability
If through-holes are formed to extend from top surface to bottom level for interconnection, then electrical connection reliability is improved, but manufacturing difficulty increases
Solution Approach 1:
The formation of through-holes is segmented into separate front-side and back-side operations. Each surface undergoes independent hole formation, filling, and planarization processes. This segmentation allows each through-hole formation step to be optimized independently, improving electrical connection reliability while making the overall manufacturing process more manageable and less difficult.
Solution Approach 2:
Dielectric regions are formed and planarized before through-hole formation. This preliminary action creates a prepared substrate with proper electrical isolation and flat surfaces, ensuring that subsequent through-hole formation and filling processes can proceed with higher reliability and reduced manufacturing difficulty.
3Reliability
If dielectric regions are formed between transistors for isolation, then transistor isolation is improved, but space for interconnection is reduced
Solution Approach 1:
By utilizing the back surface of the wafer for interconnection, the patent effectively adds another dimensional space for routing electrical connections. This relieves the spatial constraint imposed by dielectric isolation regions on the front surface, allowing adequate isolation to be maintained while still providing sufficient space for interconnection through the third dimension (back-side access).
Data Source
AI summary
A method includes forming a first CFET and a second CFET. The first CFET includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.