Stacked CFET Backside Power Nodes for Lower IR Drop
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Solution Overview
Problem
Integrated circuits (ICs) with complementary field effect transistors (CFETs) face challenges in reducing the number of power pickup cells and area occupied by circuit cells due to the conventional layout configurations, which also lead to increased IR drops and capacitive couplings between signal lines.
Innovation Solution
The implementation of back-side power nodes in the ICs, connected through top-to-bottom via-connectors, allows for reduced power pickup cells, decreased area usage, and reduced IR drops between power rails and conducting lines, while also acting as signal shields to minimize capacitive couplings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional layout configurations are used, then the IC structure is simple, but the number of power pickup cells increases and area occupied by circuit cells increases
Solution Approach 1:
The patent introduces backside power nodes in the substrate and uses top-to-bottom via-connectors to connect front-side power rails to backside power nodes, transitioning from a planar power distribution to a three-dimensional structure. This vertical connection approach reduces the area occupied by circuit cells while maintaining structural simplicity.
2Device complexity
If conventional layout configurations are used, then the IC structure is simple, but the number of power pickup cells increases
Solution Approach 1:
The patent merges the power pickup function into the backside power nodes located in the substrate, consolidating multiple power pickup operations into unified backend structures. This reduces the number of individual power pickup cells needed while keeping the overall IC structure simple through integrated design.
3Reliability
If conventional layout configurations are used, then power pickup cells are sufficient, but IR drops increase
Solution Approach 1:
By introducing backside power nodes and vertical top-to-bottom via-connectors, the patent creates short vertical current paths that reduce the length of current flow paths. This three-dimensional power distribution architecture minimizes resistance and consequently reduces IR drops, improving power supply stability while reducing energy loss.
4Device complexity
If conventional layout configurations are used, then signal line routing is simple, but capacitive couplings between signal lines increase
Solution Approach 1:
The patent introduces backside power nodes as intermediary structures that serve dual functions: power distribution and signal shielding. These backside power nodes act as mediators by providing electrostatic shielding between signal lines, reducing capacitive couplings while maintaining simple signal line routing configurations.
Data Source
AI summary
A method includes fabricating a first-type active-region semiconductor structure and second-type active-region semiconductor structure stacked with each other. The method also includes fabricating an upper source conductive segment intersecting the second-type active-region semiconductor structure at a second source region and forming a front-side power rail extending in a first direction that is conductively connected to the upper source conductive segment through a front-side terminal via-connector. The method further includes forming a top-to-bottom via-connector that passes through the substrate and conductively connects to the upper source conductive segment, forming a back-side metal layer on a backside of the substrate, and forming a back-side power node extending in the first direction that is conductively connected to the top-to-bottom via-connector.