Stacked CFET Channel Spacing for Threshold Voltage Control
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Solution Overview
Problem
Existing complementary field effect transistors (C-FET) structures face challenges in achieving optimal spacing between n-type and p-type multi-gate transistors, leading to inadequate metal gate work function metal tuning and threshold voltage control, which are critical for advanced semiconductor devices.
Innovation Solution
The proposed CFET design incorporates varying spacing between n-type and p-type field-effect transistor sheets, utilizing different semiconductor layer thicknesses to enhance metal gate work function metal tuning and threshold voltage control, achieved through precise etching and deposition processes to form isolated and strained source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform spacing is used between n-type and p-type transistor sheets, then fabrication is simplified, but metal gate work function tuning and threshold voltage control are inadequate
Solution Approach 1:
The patent applies local quality by implementing different spacing between n-type and p-type transistor sheets. Specifically, the distance between adjacent n-type sheets is set to a first value, while the distance between adjacent p-type sheets is set to a second value that is greater than the first value. This non-uniform spacing allows for optimized electrostatic control and threshold voltage tuning in different regions of the stacked transistor structure, resolving the contradiction between fabrication simplicity and manufacturing precision.
2Reliability
If larger spacing is used between transistor sheets, then electrostatic control is improved, but device area increases
Solution Approach 1:
The patent resolves this contradiction by transitioning from a two-dimensional planar layout to a three-dimensional stacked configuration. Multiple n-type and p-type transistor sheets are stacked vertically with controlled spacing, allowing improved electrostatic control through the third dimension while maintaining a compact footprint. The vertical stacking enables sufficient spacing for electrostatic control without proportionally increasing the lateral device area.
Data Source
AI summary
A device includes a first transistor and a second transistor over the first transistor. The first transistor comprises a plurality of first channel layers arranged one above another, a first gate structure wrapping around each of the plurality of first channel layers, and first source/drain regions on opposite sides of the first gate structure. The second transistor comprises a plurality of second channel layers arranged one above another, a second gate structure wrapping around each of the plurality of second channel layers, and second source/drain regions on opposite sides of the second gate structure. A distance between the first channel layers is different from a distance between the second channel layers.