Stacked CFET Nanostructure Layout for Independent Channel Width Tuning
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Solution Overview
Problem
The integration of complementary FET (CFET) devices is challenging due to the complexity of semiconductor manufacturing processes, particularly in stacking nMOS and pMOS devices, which hinders the realization of high-performance and low-power integrated circuits.
Innovation Solution
The formation of CFET structures involves vertically stacking transistors with different channel widths and materials, utilizing nanostructure transistors like GAA transistors, and employing double-patterning or multi-patterning photolithography processes to create smaller pitches, allowing for independent adjustment of transistor performance and improved design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nMOS and pMOS devices are vertically stacked to form CFET structures, then the effective channel width is maximized, but the integration complexity of fabrication increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming first and second stack structures with different semiconductor materials, selectively removing portions of these stacks to create separated nMOS and pMOS device regions, and independently processing each transistor type. This segmentation allows complex CFET fabrication to be broken down into manageable steps that can be performed with existing manufacturing capabilities.
Solution Approach 2:
Different semiconductor materials are used in different vertical regions of the stacked structure. The first stack structure contains first semiconductor material for nMOS devices, while the second stack structure contains second semiconductor material for pMOS devices. This local differentiation of material properties enables independent optimization of each transistor type's performance characteristics.
2Productivity
If double-patterning or multi-patterning photolithography processes are used to create smaller pitches, then transistor density increases, but manufacturing process complexity increases
Solution Approach 1:
Mandrel structures are formed in advance as templates before the actual transistor active areas are defined. These preliminary mandrels guide subsequent patterning steps and material deposition, enabling precise alignment and smaller pitch features to be achieved through a systematic sequence of operations rather than attempting to directly pattern the final transistor geometry.
Solution Approach 2:
The fabrication approach utilizes vertical stacking in the third dimension to achieve higher transistor density without proportionally increasing lateral pitch reduction requirements. By stacking nMOS and pMOS devices vertically, the effective channel width increases in the vertical dimension, compensating for the complexity introduced by advanced lateral patterning processes.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a bottom transistor. The bottom transistor includes a plurality of first nanostructures and a first gate structure wrapping the first nanostructures. The semiconductor structure also includes a top transistor above the bottom transistor. The top transistor includes a plurality of second nanostructures and a second gate structure wrapping the second nanostructures. The first width of one of the first nanostructures is greater than the second width of one of the second nanostructures. The semiconductor structure includes a first middle dielectric layer between the first gate structure and the second gate structure, and the first middle dielectric layer has a third width. The third width is larger than the second width.