Stacked C-FET Source/Drain Contacts With Void-Free Metal Gap Fill
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Solution Overview
Problem
Existing stacked complementary field effect transistors (C-FET) structures face challenges in forming void-free source/drain contacts in high aspect ratio openings due to early metal merging during the metal gap fill process, which affects the electrical isolation and performance of semiconductor devices.
Innovation Solution
A cyclic deposition-etch-deposition process is employed to form source/drain contacts layer-by-layer in a bottom-up manner, improving gap fill capability and achieving void-free filling in high aspect ratio openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal gap fill process is used, then manufacturing simplicity is maintained, but void formation occurs in high aspect ratio openings leading to merge issues
Solution Approach 1:
The metal gap fill process is segmented into multiple deposition steps (first metal deposition, second metal deposition) separated by an etch back step. This segmentation allows each deposition step to fill the high aspect ratio opening more effectively without forming voids, while the etch back step removes excess material and prevents merging. The segmented approach transforms a single complex filling operation into manageable stages that collectively achieve void-free filling.
Solution Approach 2:
The process employs periodic action through alternating deposition and etch back cycles. The first metal is deposited, then partially removed by etch back, followed by deposition of the second metal. This periodic sequence of depositing and selectively removing material enables precise control over the filling process, ensuring complete void elimination while maintaining proper dimensional control and preventing unwanted merges between adjacent structures.
2Productivity
If high aspect ratio openings are formed for vertical stacking, then device density is improved, but gap fill capability deteriorates leading to void formation
Solution Approach 1:
The solution uses composite material structure by forming a multi-layer metal fill structure consisting of different metal materials (first metal and second metal). Each metal layer is optimized for specific functions: the first metal provides initial gap filling, the etch back removes excess, and the second metal completes the filling and provides final structural integrity. This composite approach enables successful filling of high aspect ratio openings that would be impossible with a single material system.
Solution Approach 2:
The process changes material parameters by transitioning from a single metal deposition process to a multi-metal sequential deposition process with intermediate etch back. This parameter change includes altering the deposition material type, controlling deposition thickness at each stage, and applying selective removal. These parameter changes enable the filling process to adapt to the challenging geometry of high aspect ratio openings, achieving complete void-free filling while maintaining device density benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the formation of void-free source/drain contacts, improving the electrical isolation and performance of semiconductor devices by reducing aspect ratios and preventing metal merging issues.
Implementation Method 1
performing a first deposition process to form a first metal in the opening
Implementation Method 2
performing a second deposition process to form a second metal in the opening and over the first metal
Implementation Method 3
performing a first etching back process to the first metal until the first void is absent
Data Source
AI summary
A method includes forming a first transistor over a substrate, in which the first transistor includes first source/drain epitaxy structures; forming a second transistor over the first transistor, in which the second transistor includes second source/drain epitaxy structures; forming an opening extending through one of the second source/drain epitaxy structures and exposing a top surface of one of the first source/drain epitaxy structures; performing a first deposition process to form a first metal in the opening, in which a first void is formed in the first metal during the first deposition process; performing a first etching back process to the first metal until the first void is absent; and performing a second deposition process to form a second metal in the opening and over the first metal.