Stacked CFET Contact Isolation With Shared Dielectric Layers
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Solution Overview
Problem
The existing manufacturing processes for GAA CFET transistors are complex and costly, making it challenging to achieve controlled industrial production while meeting quality requirements and reducing process steps.
Innovation Solution
A microelectronic device architecture with superimposed transistors featuring stacked channels and coated grids, where dielectric layers serve both as insulation for channels and contacts, minimizing the number of distinct elements and process steps, and a manufacturing process that selectively forms semiconductor channels and grids with reduced complexity by using 2D materials like transition metal dichalcogenides, preserving them until the end of the process to avoid degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional GAA CFET manufacturing process is used, then transistor performance requirements are met, but the number of process steps is high and manufacturing cost is significant
Solution Approach 1:
The patent merges the formation of dielectric layers for channel insulation and contact isolation into a single integrated process. The first dielectric layer serves dual functions: insulating the first channel from the first encapsulating gate and isolating the first source contact from the second source/drain contacts. This consolidation reduces the total number of process steps while maintaining all necessary insulation functions.
Solution Approach 2:
The first dielectric layer is designed to perform multiple functions simultaneously: it acts as a gate dielectric for the first transistor and as an isolation layer for the contacts. This multi-functionality approach eliminates the need for separate dedicated isolation layers, thereby simplifying the manufacturing process.
2Reliability
If conventional GAA CFET manufacturing process is used, then quality standards are met, but process cost is significant
Solution Approach 1:
By combining multiple insulation functions into the first dielectric layer, the patent reduces the total number of deposition and etching cycles required. This directly lowers process cost while maintaining all necessary insulation functions for reliable device operation.
3Stability of the object's composition
If 2D materials are introduced early in the process, then material integrity is compromised, but process flexibility is improved
Solution Approach 1:
The patent prepares all the structural layers, dielectric layers, and contact structures before introducing the 2D material channels. This preliminary preparation of the device architecture allows the 2D materials to be introduced late in the process, minimizing their exposure to potentially damaging process conditions while still allowing for process flexibility in earlier steps.
Solution Approach 2:
The patent uses sacrificial layers and dielectric structures as intermediary elements that protect the 2D material channels during fabrication. These intermediaries allow subsequent processing steps to be performed without directly exposing or damaging the sensitive 2D materials, thereby preserving material integrity while maintaining process flexibility.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
The invention relates to a device comprising two transistors (T1, T2) stacked along z, the first transistor (T1) comprising channels (41a) stacked along z and first source and drain contacts (60Sa, 60Sd), the second transistor (T2) comprising channels (41b) stacked along z and second source and drain contacts (60Sb, 60Db), the device being characterized in that the first source (respectively drain) contact and the second source (respectively drain) contact are distinct and isolated from each other by a first dielectric gate layer (31) and by a second dielectric gate layer (35). The invention also relates to a method for manufacturing this device.