Stacked CFET S/D Contact Layout to Prevent Isolation Layer Undercut

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Solution Overview

Problem

The 2-level design of complementary field-effect transistors (CFETs) introduces processing challenges related to source and drain contacting due to their stacked arrangement, which complicates the formation of effective contacts.

Innovation Solution

A method for forming semiconductor devices with a stacked transistor structure, involving the formation of contact trenches and contacts that allow for interconnected bottom and top source/drain structures while maintaining the integrity of the contact isolation layer, using specific lithography and etching processes to ensure accurate and efficient contact formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact trenches are formed to expose both bottom and top S/D structures, then interconnection is achieved, but the contact isolation layer is removed causing material loss and undercutting

Engineering Contradiction:
Improvecontacting efficiencyVSAvoidcontact isolation layer material
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The contact formation process is segmented into two distinct approaches: first contact trenches that preserve the contact isolation layer, and second contact trenches that remove it. This segmentation allows selective exposure of S/D structures while controlling material removal, preventing unnecessary undercutting and maintaining structural integrity where the isolation layer is needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the contact isolation layer are treated differently: it is preserved in first contact trenches to prevent undercutting and maintain isolation, while selectively removed in second contact trenches to enable electrical connection. This local differentiation optimizes both protection and connectivity functions of the isolation layer.

Inventive Principle:
Principle #3Local quality

2Reliability

If the contact isolation layer is removed to form contacts, then electrical connection is enabled, but undercutting occurs reducing manufacturing precision

Engineering Contradiction:
Improveelectrical connectionVSAvoidcontact formation accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The contact isolation layer is removed only after the contact trenches are formed and only in the specific regions where electrical connection is required. This preliminary sequencing ensures that the layer serves its protective function during trench formation, then is selectively removed to enable connection without causing unwanted undercutting in other areas.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If a unified contact formation process is used for both sides of the gate structure, then process simplicity is maintained, but asymmetric device requirements cannot be met

Engineering Contradiction:
Improveprocess simplicityVSAvoiddevice configuration flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The contact formation process is made dynamic and adaptive: first contact trenches are formed across both sides to establish basic connectivity, then second contact trenches are selectively formed only where needed to remove the isolation layer. This dynamic approach allows the process to adapt to asymmetric device requirements while maintaining a systematic workflow.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4391038A1A method for forming a semiconductor device
Publication Date: 2024.06.26 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • EP4391038A1 patent drawingFigure 1
  • EP4391038A1 patent drawingFigure 2
  • EP4391038A1 patent drawingFigure 3

AI summary

The disclosure relates to a method for forming a semiconductor device, comprising: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure stacked on top of the bottom channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure, wherein the first bottom and top S/D structures are formed at a first side of the gate structure, and the second bottom and top S/D structures are formed at a second side of the gate structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts to form capped first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench exposing the first top S/D structure over the capped first bottom S/D contact; forming a second contact trench exposing the second bottom S/D contact and the second top S/D structure; and forming a first top S/D contact in the first contact trench, in contact with the first top S/D structure, over the capped first bottom S/D contact, and a second top S/D contact in the second contact trench, in contact with the second top S/D structure and the second bottom S/D contact.