Stacked CFET DVB Partial-Recess Structure for Lower Parasitic Capacitance

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Solution Overview

Problem

Complementary field effect transistors (CFETs) face performance issues due to parasitic capacitance challenges associated with process scaling, which degrade device performance.

Innovation Solution

The implementation of a deep via backside (DVB) that is partially recessed to reduce parasitic capacitance by replacing metal in non-contact areas with a dielectric material in CFET transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If process scaling is implemented to increase device density, then device integration density is improved, but parasitic capacitance increases which degrades device performance

Engineering Contradiction:

Improvedevice integration densityVSAvoidparasitic capacitance

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes metal material from non-contact areas of deep via backside structures. By selectively removing metal that does not contribute to electrical connectivity, the parasitic capacitance between the deep via and surrounding conductors is reduced while maintaining the electrical function of contact areas.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different material properties to different regions of the deep via backside structure. Contact areas retain metal material for electrical connectivity, while non-contact areas are converted to dielectric material to reduce parasitic capacitance. This local differentiation optimizes both electrical function and parasitic reduction.

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If deep via backside structures are used to support CFET architecture, then device functionality is improved, but parasitic capacitance increases which reduces device performance

Engineering Contradiction:

Improvedevice functionalityVSAvoidparasitic capacitance

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts metal from portions of the deep via backside structure where it is not needed for electrical contact. This selective removal reduces the parasitic capacitance generated by the deep via backside structure while preserving its structural support function and electrical connectivity where required.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements local quality by maintaining metal material in contact areas for electrical functionality while converting non-contact areas to dielectric material. This creates a differentiated structure that supports CFET architecture while minimizing parasitic capacitance in regions where it would be harmful.

Inventive Principle:

Principle #3Local quality

Data Source

PatentEP4626174A1Deep via backside (DVB) partial recess for capacitance reduction in complementary FET (CFET) transistors

Publication Date: 2025.10.01 INTEL CORP

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AI summary

A stacked complementary field-effect device (CFET) device includes a bottom contact region and a top contact region. A first transistor layer of a first type is over the bottom contact region and a second transistor layer of a second type is over the first transistor layer. The top contact region is over the second transistor layer. The CFET device may include a backside wall extending between the top contact region and the bottom contact region, the backside wall adjacent to the top contact region, the transistor layer, and the second transistor layer, the backside wall comprising a partially recessed portion that includes a metal material on the bottom contact region and a dielectric material over the metal material that extends up to the top contact region.