Stacked Nanostructure CFET Layout With Independent Fork-Sheet Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing while maintaining complexity and efficiency, requiring advancements in IC processing and manufacturing techniques to accommodate smaller geometries and increased functional density.
Innovation Solution
The development of complementary FET (CFET) devices with individual fork-sheet gate structures, involving the formation of epitaxial layers and gate spacers, allows for independent gate control and efficient channel formation, enabling the creation of nanostructure transistors with improved carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If geometry size is decreased to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The patent divides the transistor gate into multiple independent fork-sheet gate structures (first gate structure and second gate structure) that can be independently formed and controlled. This segmentation allows each gate to be optimized separately while maintaining overall device functionality, addressing the complexity issue by breaking down the monolithic gate into manageable segments that can be processed through separate etching and formation steps
Solution Approach 2:
The patent transitions from planar 2D transistor structures to three-dimensional vertically-stacked CFET architectures with gates extending in multiple spatial dimensions. The fork-sheet gates wrap around channel regions in a 3D configuration, enabling independent control of multiple channels from different orientations, thereby increasing functional density without proportionally increasing processing complexity
2Quantity of substance
If functional density is increased with smaller geometries, then more devices fit per chip area, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed in advance before the final gate structures. The first and second gate structures are prepared through sequential spacer formation and etching processes, allowing complex 3D gate geometries to be created through predetermined, standardized manufacturing steps rather than direct complex patterning
Solution Approach 2:
The patent introduces intermediary sacrificial layers and spacer materials that facilitate the formation of complex fork-sheet gate structures. These intermediary elements serve as templates and guides during manufacturing, enabling precise formation of the independent gate structures through standard deposition and etching processes without requiring direct complex patterning
Data Source
AI summary
An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.