Stacked CFET Gate Structure for Current Matching and Lower Capacitance
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Solution Overview
Problem
Existing semiconductor devices, particularly CFET structures, have not been entirely satisfactory in achieving optimal performance and area-saving benefits, as they lack the ability to independently adjust the performance of stacked devices without altering channel dimensions or increasing capacitance.
Innovation Solution
The configuration of a CFET structure with one device as an active device and the other as an inactive device, utilizing a dielectric gate structure instead of a metal gate structure, allows for independent adjustment of performance by skewing current levels between complementary devices, reducing chip area by up to 50% and lowering capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If CFET structures are used to achieve higher device density and area-saving benefits, then chip area is reduced, but the ability to independently adjust performance is lost and capacitance increases
Solution Approach 1:
The patent divides the gate structure into two separate parts: a metal gate structure for the active device and a dielectric gate structure for the inactive device. This segmentation allows independent adjustment of each device's performance characteristics while maintaining the stacked CFET configuration for area savings.
Solution Approach 2:
The patent applies different gate structure types to different devices within the same stack: the active device receives a metal gate structure for high performance, while the inactive device receives a dielectric gate structure for reduced capacitance and skew control. This local differentiation enables independent performance optimization without compromising the overall area benefit.
2Power
If metal gate structures are used in both stacked devices, then active device performance is maximized, but capacitance between devices increases and independent adjustment is prevented
Solution Approach 1:
The patent extracts the metal gate structure from both devices and assigns it only to the active device where it is needed for maximum performance. The inactive device has its metal gate structure replaced with a dielectric gate structure, removing the source of excessive capacitance while preserving the area-saving stacked configuration.
Solution Approach 2:
The patent changes the gate structure parameter from metal to dielectric material for the inactive device. This material parameter change reduces the capacitance between the stacked devices while allowing the active device to maintain its metal gate structure for optimal performance.
3Reliability
If channel dimensions are altered to adjust device performance, then current levels can be matched, but device density and area-saving benefits are compromised
Solution Approach 1:
The patent introduces dynamic adjustability through independent gate structure selection for each device in the stack. This allows performance parameters like current levels to be tuned independently without altering the physical channel dimensions or stacking configuration, preserving area savings while enabling current matching.
Data Source
AI summary
A semiconductor device includes an active gate structure disposed over a substrate; first source/drain features disposed at two opposite sides of the active gate structure; a dielectric gate structure disposed over the substrate, the dielectric gate structure and the active gate structure stacked one over another along a vertical direction perpendicular to the substrate; and second source/drain features disposed at two opposite sides of the dielectric gate structure, where the first source/drain features and the second source/drain features are of different conductivity types.