Stacked CFET Gate Formation Without Lateral Gate Extensions
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Solution Overview
Problem
Existing methods for forming a sequential complementary field-effect transistor (CFET) with electrically connected top and bottom gate electrodes are complicated, particularly in achieving a common gate electrode connection without increasing parasitic capacitance.
Innovation Solution
A method involving the formation of a bottom FET device with a bottom gate electrode, a bonding layer, and a top FET device with a fin structure, where isotropic etching is used to remove the bonding layer and form a common gate electrode in the space underneath the channel layer, allowing for a top-to-bottom gate electrode connection without lateral side gate extensions, and using a second spacer layer as an etch mask to confine the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sequential CFET is formed with separate gate electrodes connected by a vertical via, then electrical connection between gates is achieved, but the process becomes complicated with increased manufacturing difficulty
Solution Approach 1:
The patent merges the top gate electrode formation process with the bottom gate electrode connection process. Instead of separately forming a vertical via and then filling it with gate material, the method forms a common gate electrode structure that simultaneously serves as the top gate for the first FET and connects to the bottom gate of the second FET. This is achieved by forming a gate electrode over the bonding layer, removing portions of the bonding layer to expose the bottom gate electrode, and forming additional gate electrode material in contact with both the channel layer and the bottom gate electrode, thereby eliminating the need for separate via formation steps.
2Device complexity
If a common gate electrode is formed by removing placeholder gate stacks via inter-level etch, then a single gate stack is formed, but the etching process requires high aspect ratio and specific selectivity making the process difficult
Solution Approach 1:
The patent performs preliminary actions by forming the gate electrode structure and bonding layer configuration before final gate electrode completion. Specifically, a gate electrode is formed over the bonding layer, and portions of the bonding layer are removed to expose the bottom gate electrode. This preliminary configuration allows subsequent formation of gate electrode material that naturally creates the connection path, avoiding the need for complex high aspect ratio etching with specific selectivity requirements that would be needed if placeholder stacks were removed first.
3Reliability
If lateral side gate extensions are used to connect top and bottom gates, then electrical connection is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from lateral connection (in the plane) to vertical connection (out of plane). Instead of extending gate electrodes laterally to connect top and bottom gates, which would increase parasitic capacitance, the method forms a vertical connection path through the bonding layer. The gate electrode structure extends vertically to contact the bottom gate electrode, creating a compact connection that minimizes parasitic capacitance while achieving electrical connectivity between the top and bottom gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of a common gate electrode with increased cross-sectional area, reducing resistivity and parasitic capacitance, while maintaining the area efficiency of the CFET device.
Implementation Method 1
forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity
Implementation Method 2
epitaxially growing source/drain bodies on the exposed end surfaces of the channel layer
Data Source
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AI summary
The disclosure relates to a method for forming a stacked field-effect transistor device, comprising: forming a bottom FET device (100) comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device (200) on the bonding layer, comprising: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion (230) exposing the fin structure portion; forming a lower gate cavity portion (232) exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode (238) in the upper and lower gate cavity portions.