Stacked CFET Source/Drain Isolation for Reliable Vertical Integration
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Solution Overview
Problem
Current CFET technologies face challenges in independently growing nFET and pFET source/drain epitaxy while maintaining vertical integration and electrical disconnection, leading to device shorting and reliability issues due to the close proximity of upper and lower device source/drain regions.
Innovation Solution
The formation of CFET structures with stacked and electrically isolated source/drain regions, utilizing an L-shaped combination of vertical and horizontal isolation elements to separate the epitaxial regions, allowing contacts to pass through to buried power rails without compromising isolation layer integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked CFET structures are used to achieve vertical integration, then device density is improved, but electrical isolation between upper and lower source/drain regions becomes difficult to maintain
Solution Approach 1:
The isolation structure is segmented into two distinct components: a vertical isolation element extending upward from the lower source/drain region, and a horizontal isolation element extending laterally from the vertical element. This segmentation allows each component to perform its isolation function independently while working together to provide complete electrical separation between upper and lower CFET source/drain regions, resolving the contradiction between maintaining vertical integration for density and ensuring electrical isolation for reliability
Solution Approach 2:
The L-shaped isolation structure acts as an intermediary element positioned between the upper and lower source/drain regions. This intermediate structure provides a physical and electrical barrier that prevents direct contact and potential shorting between the stacked CFET devices, enabling both vertical integration and reliable electrical isolation to coexist
2Adaptability or versatility
If source/drain epitaxy is grown for both nFET and pFET, then device functionality is improved, but cross-contamination between epitaxial regions increases
Solution Approach 1:
The epitaxial growth process is segmented into separate sequential steps: first growing the lower source/drain region, then forming the L-shaped isolation structure, and finally growing the upper source/drain region. This segmentation in the growth process prevents cross-contamination between nFET and pFET epitaxial materials while still enabling both device types to function, as each epitaxial region is formed in isolation without direct contact with the other
3Power
If contacts are extended through to substrate for buried power rails, then power delivery is improved, but isolation layer integrity is compromised
Solution Approach 1:
The vertical isolation element is formed in advance, extending upward from the lower source/drain region before the upper contact is formed. This preliminary action ensures that when the upper contact is subsequently created to reach the substrate for buried power rail connection, the isolation structure is already in place to guide and protect the isolation layer integrity, allowing power delivery without compromising isolation
Data Source
AI summary
A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.