Stacked GAA CFET Layout With Crystal Orientation Mobility Tuning
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Solution Overview
Problem
Existing CMOS transistors occupy significant area due to the need for balanced performance between PFETs and NFETs, with PFETs often being upsized to compensate for lower carrier mobility, leading to increased circuit cell area.
Innovation Solution
A stacked gate-all-around (GAA) CFET design with first and second GAA FETs having different crystal orientations to enhance carrier mobility, allowing for separate fabrication and reduced area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PFETs are upsized to compensate for lower carrier mobility, then PFET performance is improved, but CMOS transistor circuit cell area increases
Solution Approach 1:
The patent transitions from planar transistor arrangements to a three-dimensional stacked configuration where NFET and PFET are vertically integrated. This vertical stacking allows both transistor types to share the same footprint area, effectively halving the circuit cell area while maintaining balanced performance through optimized individual transistor dimensions in the vertical dimension
Solution Approach 2:
The patent changes the crystal orientation parameter of the semiconductor slabs from conventional <100> to <110> orientation. This parameter change increases carrier mobility in both NFET and PFET, allowing PFET to achieve balanced performance without requiring area increase, thus resolving the contradiction between PFET performance and circuit cell area
2Reliability
If both NFET and PFET are included in each CMOS transistor, then power savings and noise immunity are improved, but circuit cell area increases
Solution Approach 1:
The patent merges NFET and PFET into a single stacked CMOS transistor unit, where both transistor types are vertically integrated and share common structures such as the semiconductor slab and isolation layers. This merging maintains the functional benefits of complementary CMOS (power savings and noise immunity) while reducing the overall circuit cell area by eliminating redundant lateral spacing and shared infrastructure
3Reliability
If PFETs are sized-up to provide balanced performance, then performance balance is improved, but device complexity increases
Solution Approach 1:
The patent changes the fundamental parameter of crystal orientation from <100> to <110> in both NFET and PFET. This uniform parameter change across both transistor types increases carrier mobility systematically, allowing balanced performance to be achieved through standardized manufacturing processes rather than complex individual sizing adjustments, thus reducing device complexity
Data Source
AI summary
A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor slab with a channel region and a first surface. A first gate structure surrounds the channel region in the first GAA FET, and a second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, a first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor slab in the second GAA FET has a different orientation for improved carrier mobility.