Stacked CFET Nanowire Structure With Isolated Source/Drain Regions
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Solution Overview
Problem
Conventional FinFETs and CFETs face limitations in increasing working current and device density due to small channel volumes and poor performance, particularly with the FinFET with a gate-all-around (GAA) structure and complementary fin field-effect transistors (CFETs) formed by existing processes.
Innovation Solution
A semiconductor structure and fabrication method involving a substrate with discrete nanowires, source/drain layers, and an isolation layer, where the first and second source/drain layers are formed in specific openings with controlled volumes, and an isolation layer is used to electrically isolate them, enhancing the performance of complementary fin field-effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFET with GAA structure is used to increase channel volume, then working current increases, but device density cannot be further increased
Solution Approach 1:
The patent transitions from planar FinFET to three-dimensional GAA structure, then to vertically stacked CFET architecture. By stacking N-type and P-type GAA pairs vertically, the invention achieves higher device density while maintaining the high working current benefits of GAA through full channel coverage and increased effective channel volume.
Solution Approach 2:
The patent implements nested structure where N-type and P-type GAA pairs are vertically stacked one over another, with each GAA pair containing nanowires surrounded by gate structures. This nested arrangement allows both N-type and P-type transistors to share the same vertical space, dramatically increasing device density while maintaining individual transistor performance.
2Productivity
If CFET with vertically stacked GAA pairs is formed by existing processes, then device density increases, but transistor performance becomes poor
Solution Approach 1:
The patent applies different materials and structures to different regions: silicon-based nanowires for N-type channels, III-V semiconductor nanowires for P-type channels, selective dielectric materials for isolation, and tailored source/drain materials (silicon phosphide, silicon germanium, etc.) for each region. This localized optimization ensures high performance for each transistor type while maintaining high device density through vertical stacking.
Solution Approach 2:
The patent controls critical parameters including nanowire diameter (5-20nm), spacing between nanowires, gate structure dimensions, source/drain layer composition ratios, and doping concentrations. By precisely controlling these parameters, the invention achieves optimal transistor performance while maintaining the high device density enabled by vertical stacking architecture.
3Ease of manufacture
If source/drain layers are formed without volume control, then fabrication is simpler, but performance is limited
Solution Approach 1:
The patent performs preliminary actions by forming isolation layers between N-type and P-type source/drain regions before completing source/drain layer formation, and by pre-defining opening dimensions and nanowire configurations. This preliminary structuring enables subsequent source/drain layer deposition to achieve precise volume control, which enhances driving current while maintaining fabrication feasibility through standardized process steps.
Data Source
AI summary
Semiconductor structure and formation method are provided. A method of forming a semiconductor structure includes providing a dielectric layer on a substrate, the dielectric layer including a first region and a second region under the first region, the first region including discrete first initial nanowires, and the second region including discrete second initial nanowires; etching the dielectric layer and the first initial nanowires in the first region to form a first opening in the first region, and forming first nanowires from the first initial nanowires; etching the dielectric layer at a bottom of the first opening and the second initial nanowires to form a second opening in the second region, and forming second nanowires from the second initial nanowires; forming a second source/drain layer in the second opening; forming an isolation layer on the second source/drain layer; and forming a first source/drain layer in the first opening.