Stacked CFET Capacitance Cell Layout for Noise-Induced Malfunctions
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Solution Overview
Problem
Current semiconductor integrated circuits face challenges with noise-induced malfunctions due to increased noise levels and reduced noise immunity, particularly with the use of three-dimensional transistors, where no effective capacitance cells utilizing complementary FETs (CFETs) have been examined.
Innovation Solution
A layout structure for a capacitance cell is provided using CFETs, incorporating three-dimensional transistors of different conductivity types stacked vertically, with specific connections and configurations to reduce the area and enhance capacitance performance, including configurations where transistors of the same conductivity type are used with dummy gate interconnects to facilitate doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistors are used to improve integration degree and operating speed, then productivity and speed are improved, but noise increases and noise immunity decreases causing circuit malfunctions
Solution Approach 1:
The patent converts the harmful noise effect into a beneficial decoupling function by utilizing the inherent capacitance between power supply lines. The decoupling capacitance cell captures noise on power supply lines and converts it into useful charge storage, transforming the noise problem into a benefit for stabilizing power supply voltage and improving noise immunity while maintaining high operating speed.
2Reliability
If decoupling capacitance is provided between power supplies to prevent noise-induced malfunctions, then reliability is improved, but device area increases
Solution Approach 1:
The patent merges the decoupling capacitance function with the existing CFET structure by utilizing the capacitance inherently formed between the first and second power supply lines. Instead of adding a separate capacitance component, the design combines the capacitance function with the transistor power supply connections, significantly reducing the area required for the decoupling capacitance cell while maintaining effective noise immunity.
Solution Approach 2:
The patent makes the power supply lines serve multiple functions: they provide power to the transistors and simultaneously form the decoupling capacitance structure. The first and second power supply lines are used both for supplying power to the source/drain regions and for creating the capacitance that filters noise, eliminating the need for dedicated capacitance components and reducing overall cell area.
3Ease of manufacture
If standard capacitance cell structures are used, then ease of manufacture is maintained, but area efficiency is poor and capacitance performance is insufficient for CFET-based circuits
Solution Approach 1:
The patent changes the fundamental parameters of the capacitance cell by using three-dimensional stacked CFETs instead of planar transistors. The vertical stacking configuration and the specific connection of source/drain regions to power supply lines create a new capacitance formation mechanism that achieves better area efficiency and capacitance performance while remaining compatible with existing manufacturing processes for CFETs.
Data Source
AI summary
A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.