Vertically Stacked CFET Structure Using Wafer Bonded N/P Isolation
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Solution Overview
Problem
The challenge in semiconductor integrated circuits is to further improve nanosheet FETs for higher device density, performance, and lower costs, particularly in three-dimensional designs, where existing technologies face issues with fabrication and design complexity.
Innovation Solution
The development of vertically stacked complementary field effect transistors (CFETs) is achieved by epitaxially growing nanosheet FETs on different substrates and bonding them using wafer bonding technology, allowing for optimized channel orientations and reduced leakage paths, with the use of dielectric bonding layers for isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanosheet FETs are scaled down to increase device density, then functional density increases, but fabrication complexity and design challenges worsen
Solution Approach 1:
The patent transitions from planar FET designs to three-dimensional vertically stacked CFET structures. By stacking n-channel and p-channel FETs vertically on the same footprint, the device density increases while maintaining manageable fabrication complexity through systematic process integration.
Solution Approach 2:
The invention divides the CFET fabrication process into distinct modules: forming n-channel FETs on first substrates, forming p-channel FETs on second substrates, bonding the substrates together, and then performing common processing steps. This segmentation allows independent optimization of each FET type and simplifies the overall fabrication complexity.
2Quantity of substance
If vertically stacked CFETs are formed to increase device density, then functional density improves, but leakage paths between channels increase
Solution Approach 1:
The patent removes substrate material between the bonded regions to create isolated channels. By extracting the substrate in non-bonded areas, leakage paths between n-channel and p-channel are eliminated, while the bonded regions maintain electrical isolation through the bonding interface.
Solution Approach 2:
The bonding structure serves as an intermediary between the n-channel and p-channel FETs. It provides mechanical support and electrical isolation, preventing direct leakage paths while allowing the vertically stacked configuration to achieve high device density.
3Reliability
If wafer bonding technology is used to form vertically stacked CFETs, then device performance improves through optimized channel orientations, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary fabrication of n-channel and p-channel FETs on separate substrates before bonding. This allows channel orientations, doping profiles, and device geometries to be optimized independently for each transistor type, improving overall device performance while the bonding process integrates them into a compact stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by optimizing mobility and reducing defects, providing a flexible and efficient method for forming N/P channel isolation structures in stacked CFETs, thus improving device density and reducing fabrication challenges.
Implementation Method 1
bonding the second substrate to the first substrate using wafer bonding technology
Implementation Method 2
epitaxially growing nanosheet FETs on different substrates
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N/P channel properties, provide a simple way to form the N/P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.