Stacked CFET Power Rail Layout for Lower Coupling and Resistance

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Solution Overview

Problem

Integrated circuits (ICs) with complementary field effect transistors (CFETs) face challenges in optimizing power connections and signal shielding due to the positioning of power rails and signal lines in the front-side and back-side conductive layers, leading to increased resistance and capacitive couplings between cells.

Innovation Solution

The IC design incorporates a stacked configuration of CFETs with power rails and signal lines in both conductive layers, where the source terminals of PMOS and NMOS transistors are connected to supply voltages through optimized via-connectors, reducing resistance and enhancing inter-cell signal shielding by interlacing power and signal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power rails and signal lines are positioned in front-side and back-side conductive layers, then IC device functionality is achieved, but resistance increases and signal shielding deteriorates

Engineering Contradiction:

Improvepower connection qualityVSAvoidcapacitive coupling between cells

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent utilizes the third dimension (vertical stacking) by implementing CFET devices with upper and lower transistors stacked above each other. Power rails and signal lines are distributed across front-side and back-side conductive layers at different vertical positions, transforming a two-dimensional layout problem into a three-dimensional spatial arrangement that reduces parasitic coupling while maintaining electrical connectivity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive interconnect structure is segmented into multiple independent layers (front-side conductive layer and back-side conductive layer) positioned at different vertical levels. This segmentation allows power rails and signal lines to be separated in the vertical dimension, reducing capacitive coupling between adjacent conductors while providing multiple independent pathways for electrical connections.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If conventional power rail arrangement is used, then manufacturing is simplified, but resistance increases and power connection efficiency deteriorates

Engineering Contradiction:

Improveconductive layer configurationVSAvoidpower connection resistance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent moves power rail connections from a single-plane (2D) arrangement to a multi-layer stacked configuration (3D). By utilizing both front-side and back-side conductive layers with vertical via connections, the power delivery network achieves lower effective resistance through parallel conduction paths without significantly complicating the manufacturing process, as the stacked CFET structure inherently requires this multi-layer approach.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If active-region semiconductor structures are widened, then device performance improves, but capacitive coupling between cells increases

Engineering Contradiction:

Improvedevice performanceVSAvoidstray capacitive couplings

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent addresses the coupling issue by exploiting the vertical dimension. Active-region semiconductor structures can be widened in the horizontal plane to improve device performance while the stacked CFET configuration and multi-layer conductive arrangement isolate adjacent cells vertically, reducing stray capacitive couplings between cells despite the increased horizontal area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Device complexity

If signal lines are routed in single layer, then routing complexity is reduced, but signal integrity deteriorates due to increased coupling

Engineering Contradiction:

Improvesignal line routingVSAvoidsignal integrity

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The signal line routing is segmented across two separate conductive layers (front-side and back-side). This segmentation allows signal lines to be distributed in the vertical dimension, reducing capacitive coupling between adjacent signal lines while maintaining relatively simple routing within each individual layer. The multi-layer approach improves signal integrity without significantly increasing routing complexity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11764154B2Power rail and signal line arrangement in integrated circuits having stacked transistors

Publication Date: 2023.09.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail. The integrated circuit device further includes a drain conductive segment connected to either the front-side signal line or the back-side signal line.