Stacked CFET Power Rail Layout for Lower Resistance Shielding
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Solution Overview
Problem
Existing integrated circuits (ICs) with complementary field effect transistors (CFETs) face challenges in optimizing power connections and signal line configurations, leading to increased resistance and restrictions on active-region semiconductor structures, which affect device performance and signal shielding.
Innovation Solution
The ICs employ a dual-layer power rail and signal line arrangement, utilizing front-side and back-side conductive layers to improve power connections, reduce resistance, and enhance signal shielding by interlacing power rails with signal lines, thereby optimizing the positioning of power rails and signal lines within the ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power rails and signal lines are arranged in a single conductive layer, then the layout is simpler, but resistance increases and signal shielding is reduced
Solution Approach 1:
The patent transitions from a single-layer conductive arrangement to a multi-layer stacked CFET architecture where power rails and signal lines are distributed across front-side and back-side conductive layers. This dimensional change enables improved signal shielding and reduced resistance by separating power and signal paths in the vertical dimension while maintaining planar simplicity in each individual layer.
2Reliability
If active-region semiconductor structures are extended in width, then device performance improves, but manufacturing complexity and restrictions increase
Solution Approach 1:
The stacked CFET architecture utilizes the vertical dimension by forming upper and lower FETs at different heights above the substrate. This enables active-region semiconductor structures to achieve enhanced performance through vertical stacking rather than horizontal extension, thereby avoiding manufacturing restrictions associated with width extensions while maintaining improved device performance.
3Reliability
If power connections are optimized in conventional layouts, then resistance decreases, but signal line configurations become restricted
Solution Approach 1:
The multi-layer conductive structure distributes power rails across front-side and back-side layers, enabling optimized power connections with reduced resistance through vertical pathways. Simultaneously, signal lines can be configured independently in each layer without being constrained by power rail positions, thereby maintaining configuration flexibility and adaptability.
Solution Approach 2:
The conductive system is segmented into multiple independent layers (front-side and back-side conductive layers), allowing power connections and signal line configurations to be optimized separately in each layer. This segmentation enables reduced resistance in power paths while maintaining flexibility in signal routing without mutual interference.
Data Source
AI summary
A method includes fabricating a first-type active-region semiconductor, depositing a layer of dielectric material covering the first-type active-region semiconductor structure, and fabricating a second-type active-region semiconductor structure atop the layer of dielectric material. The method includes forming a front-side power rail and a front-side signal line extending in the first direction in a front-side metal layer overlying a first insulating material that covers the first-type active-region semiconductor. The front-side power rail is conductively connected to a second source conductive segment intersecting the second-type active-region semiconductor structure. The method includes forming a back-side metal layer on a backside of the substrate, and forming a back-side power rail and a back-side signal line extending in the first direction in the back-side metal layer. The back-side power rail is conductively connected to a first source conductive segment intersecting the first-type active-region semiconductor structure.