Vertically Stacked CFET with Segmented Gate Electrodes
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Solution Overview
Problem
The challenge in forming vertically stacked complementary-FET devices with independent gate control is the difficulty in implementing a replacement gate process due to space constraints in nano-sheet devices, particularly in balancing threshold voltages for CMOS devices using different gate materials.
Innovation Solution
A method involving the formation of a stack of semiconductor material layers with spacers and a sacrificial gate structure, followed by selective removal and deposition of conductive materials to create independent gate electrodes for P-type and N-type transistors, allowing for electrical isolation and independent control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a replacement gate process is used to form different gate materials for PMOS and NMOS devices, then threshold voltages can be balanced, but space constraints in nano-sheet devices make it difficult to implement
Solution Approach 1:
The gate structure is segmented into two independent gates (first gate and second gate) positioned at different vertical levels. Each gate can be formed with different materials independently, allowing threshold voltage balancing for PMOS and NMOS devices without requiring a complex replacement gate process. The segmentation enables separate control of each transistor type within the vertically stacked CFET structure.
Solution Approach 2:
The patent transitions from a planar gate configuration to a three-dimensional vertically stacked configuration. By positioning gates at different vertical levels (first gate at a lower level, second gate at a higher level), the structure utilizes the vertical dimension to accommodate independent gate control for both PMOS and NMOS devices within a compact footprint, overcoming the space constraints that prevent conventional replacement gate processes.
2Productivity
If vertically stacked CFET structure is used to increase device density, then circuit integration is improved, but independent gate control for different transistor types becomes difficult
Solution Approach 1:
The vertically stacked CFET structure is segmented into distinct upper and lower regions, each containing its own gate electrode (second gate for upper region, first gate for lower region). This segmentation allows independent electrical control of each transistor type while maintaining the high-density vertical stacking configuration. Each gate can be independently biased to control its respective channel without interfering with the other transistor type.
Solution Approach 2:
A gate dielectric layer is introduced as an intermediary between the first gate and the upper region semiconductor material, and between the second gate and the lower region semiconductor material. This gate dielectric enables independent electrical control of each gate while maintaining the vertically stacked configuration, allowing each gate to independently modulate its respective channel without direct electrical interference.
3Reliability
If different gate materials are used for PMOS and NMOS, then device performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into separate formation steps for the first gate and second gate. Different conductive materials can be deposited for each gate using independent deposition processes, allowing optimization of each transistor type's performance without requiring a complex replacement gate process. The segmented approach simplifies manufacturing by enabling parallel or sequential formation of different gate materials.
Solution Approach 2:
By utilizing the vertical dimension to position gates at different levels, the patent enables different gate materials to be formed without requiring lateral separation or complex replacement processes. The vertical stacking allows direct formation of different conductive materials at different heights, reducing manufacturing complexity while maintaining performance optimization.
Data Source
AI summary
A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.