Stacked CFET Structure for Finer Semiconductor Miniaturization
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Solution Overview
Problem
Current semiconductor devices, particularly complementary field effect transistors (CFETs), fail to meet the demand for further miniaturization and finer microfabrication required by recent technological advancements.
Innovation Solution
A semiconductor device design that includes a stacked transistor structure with multiple layers of nanowires and conductivity type-specific regions, allowing for the overlap of transistors of the same conductivity type, thereby enhancing miniaturization and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional CFET stacking is used, then device integration is achieved, but further miniaturization and finer microfabrication are not sufficiently enabled
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional stacking, where transistors are arranged in multiple layers vertically over the substrate. This dimensional change enables further miniaturization by utilizing the vertical space rather than only horizontal plane, allowing finer microfabrication while maintaining device functionality
Solution Approach 2:
The patent implements nested transistor structures where transistors of the same conductivity type are overlapped in vertical stacking (e.g., first transistor over third transistor, second transistor over fourth transistor). This nesting approach allows multiple transistors to occupy the same footprint area in different vertical layers, achieving finer microfabrication and higher integration density
2Volume of moving object
If transistors are overlapped to enhance miniaturization, then device compactness is improved, but transistor operation reliability must be maintained
Solution Approach 1:
The patent segments transistors into distinct conductivity types (first and third transistors of first conductivity type, second and fourth transistors of second conductivity type) arranged in separate vertical layers. This segmentation allows independent control and optimization of each transistor layer, maintaining operational reliability while achieving compact overlapping structures
Solution Approach 2:
The patent applies local quality by providing conductivity type-specific regions and gate electrodes tailored to each transistor's specific conductivity type and vertical position. Each transistor layer has optimized local characteristics (gate work function, channel material, doping profiles) to ensure reliable operation despite the compact overlapping arrangement
Data Source
AI summary
A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.