Stacked CFET Layout With Shared Gates for Lower Interconnect Power
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Solution Overview
Problem
Integrated circuits face challenges with shrinking sizes, area occupation by nano-sheet structures, and complex interconnections of complementary field-effect transistors (CFET) leading to high power consumption.
Innovation Solution
The design incorporates complementary field-effect transistors with transistors of different conductivity types on alternating layers, sharing gate structures to simplify signal routing and reduce the number of conductive traces, thereby minimizing area usage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors of different conductivity types are arranged on alternating layers with shared gate structures, then device complexity and interconnection complexity are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional stacked architecture, placing transistors of different conductivity types on alternating layers vertically. This dimensional change allows N-type and P-type transistors to share gate structures horizontally, reducing interconnection complexity while requiring precise vertical layer alignment during manufacturing.
Solution Approach 2:
The patent merges N-type and P-type transistors by having them share common gate structures. Instead of separate gate structures for each transistor type, the design combines them so that a single gate structure controls both N-type and P-type transistors on adjacent layers, thereby reducing overall device complexity and interconnection requirements.
2Productivity
If nano-sheet structures are used to reduce transistor size, then integration density increases, but area occupation by individual structures increases
Solution Approach 1:
The patent utilizes vertical stacking of nano-sheet structures across multiple layers to achieve high integration density. By arranging transistors vertically in alternating N-type and P-type layers, the design packs more functional units into a smaller planar footprint, effectively increasing integration density while managing the area occupation of individual nano-sheet structures.
3Adaptability or versatility
If complex interconnections are used to connect CFET transistors, then device functionality is achieved, but power consumption increases
Solution Approach 1:
The patent combines N-type and P-type transistors into complementary field-effect transistor (CFET) pairs that share gate structures. This merging reduces the number of separate interconnections needed compared to traditional separate transistor arrangements, thereby reducing power consumption while maintaining full device functionality through the complementary transistor pairs.
Data Source
AI summary
An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.