Stacked CFET Transistor Layout for Smaller Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Complementary Field Effect Transistors (CFETs) made by laminating P-channel and N-channel transistors result in large chip sizes due to unused transistors not being electrically operated, hindering miniaturization.
Innovation Solution
A semiconductor device design featuring a first transistor with dual channel semiconductor layers and a second transistor with dual source and drain semiconductor layers, along with a manufacturing method that forms these layers simultaneously, allowing for a compact CFET structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If CFET is made by laminating P-channel and N-channel transistors with electrically connected gate electrodes, then driving capability is improved, but chip size becomes large due to unused transistors not being electrically operated
Solution Approach 1:
The transistor structure is segmented into multiple independent transistor units within a single CFET device. Each unit contains channel semiconductor layers, source and drain semiconductor layers, and gate electrodes. By segmenting the structure, the patent enables selective electrical operation of individual transistor units, allowing unused transistors to be excluded from operation while maintaining compact integration. This resolves the contradiction by allowing high driving capability through multiple transistors while reducing chip size through selective operation of only necessary units.
2Productivity
If multiple channel semiconductor layers are formed simultaneously with source and drain semiconductor layers, then manufacturing efficiency is improved, but manufacturing precision becomes difficult to control
Solution Approach 1:
The patent applies preliminary action by forming a gate insulating film on the substrate before forming channel semiconductor layers. This preliminary layer provides a controlled foundation that enables subsequent simultaneous formation of multiple channel semiconductor layers with precise thickness and positioning. The gate insulating film acts as a reference layer that guides the formation process, ensuring manufacturing precision is maintained even when multiple layers are formed simultaneously in one process step.
Data Source
AI summary
A semiconductor device includes a substrate, and a first transistor including a first channel semiconductor layer provided on the substrate, a pair of first source and drain semiconductor layers provided on the substrate and sandwiching the first channel semiconductor layer, a first gate electrode disposed between the pair of first source and drain semiconductor layers, the first gate electrode and the first channel semiconductor layer sandwiching a first gate insulating film, a second channel semiconductor layer provided over and spaced apart from the first channel semiconductor layer, a pair of second source and drain semiconductor layers provided over the pair of first source and drain semiconductor layers and sandwiching the second channel semiconductor layer, and a second gate electrode disposed between the pair of second source and drain semiconductor layers, the second gate electrode and the second channel semiconductor layer sandwiching a second gate insulating film.