Stacked CFET Fin Structure With Split Gates and Channel Materials
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Solution Overview
Problem
The semiconductor industry faces challenges in forming complementary field effect transistors (FETs) in a stacked configuration, particularly in using different channel materials for n-type and p-type FETs, which affects device performance and integration density.
Innovation Solution
The use of FinFET processing to form a stacked CFET device with different channel materials for n-type and p-type FETs, allowing for enhanced electron mobility and logic performance, along with hybrid fin configurations and gate separation structures, enabling monolithic and sequential configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different channel materials are used for n-type and p-type FETs in a stacked configuration, then electron mobility and logic performance are enhanced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into separate n-type and p-type FET regions with distinct channel materials (e.g., SiGe for n-type, Si for p-type). This segmentation allows each transistor type to have optimized material properties while maintaining a stacked configuration, resolving the contradiction between performance enhancement and manufacturing complexity by enabling independent material selection for each device type.
Solution Approach 2:
The patent implements local quality by assigning different channel materials to specific regions: n-type FETs receive materials with higher electron mobility (like SiGe) while p-type FETs use materials optimized for hole mobility (like Si). This localized material differentiation enhances overall device performance without requiring uniform complexity across the entire wafer, as each region is optimized for its specific function.
2Reliability
If different channel materials are used for n-type and p-type FETs, then electron mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediary layers and buffer structures between different channel materials to facilitate controlled deposition and reduce manufacturing precision requirements. These intermediary layers act as transition zones that accommodate the different crystal structures and lattice constants of SiGe and Si, enabling precise material deposition without requiring extremely tight process control.
Solution Approach 2:
The patent employs parameter changes by systematically varying deposition conditions (temperature, pressure, gas flow rates) during the formation of different channel materials. By dynamically adjusting these parameters during manufacturing, the process accommodates the different material properties of SiGe and Si, reducing the overall precision requirements compared to depositing both materials under identical fixed conditions.
3Reliability
If hybrid fin configurations and gate separation structures are implemented, then logic performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the n-type and p-type FET structures into a single stacked configuration with shared components (such as common source/drain regions and isolation structures). This merging reduces the overall device complexity compared to fully separate implementations, while still maintaining the performance benefits of different channel materials and hybrid fin configurations through the integrated gate separation structures.
Solution Approach 2:
The patent transitions from planar to three-dimensional stacked configurations, utilizing the vertical dimension to separate n-type and p-type FETs. This dimensional change allows for gate separation structures and hybrid fin configurations that improve logic performance without proportionally increasing planar device complexity, as the additional structures are arranged in the vertical rather than lateral direction.
Data Source
AI summary
A method for forming complementary FinFET (CFET) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. In another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. A CFET device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.