Stacked GAA CFET Threshold Tuning With Work Function Metals

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Solution Overview

Problem

Current technologies face challenges in providing multiple threshold voltages for n-type and p-type FETs in advanced semiconductor devices, particularly at nodes beyond 5 nm, which affects device performance and scalability.

Innovation Solution

The implementation of a CFET structure with multiple voltage thresholds, where upper and lower FET devices are isolated by a dielectric layer, and each FET has distinct work function metals to achieve different voltage thresholds, enabling optimized device performance and scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional planar FET structures are used, then manufacturing process is simpler, but device performance and scalability at 5 nm node and beyond deteriorates

Engineering Contradiction:
Improvedevice performanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D FET structures to three-dimensional gate-all-around FET structures where the gate completely surrounds the channel in 3D space. This dimensional change enables superior electrostatic control and scaling to 5 nm node and beyond, directly resolving the contradiction between maintaining simple manufacturing and achieving high device performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements stacked FET structures where nFET and pFET devices are vertically nested one on top of the other, sharing common source and drain regions. This nesting approach increases device density and performance while managing the complexity through systematic vertical integration rather than horizontal expansion.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Use of energy by moving object

If single threshold voltage is used for all FETs, then device structure is simpler, but switching delay and power efficiency cannot be optimized

Engineering Contradiction:
Improvepower efficiencyVSAvoidthreshold voltage control
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies different work function metals to different FET devices within the same integrated structure. Specifically, nFET devices receive one work function metal while pFET devices receive a different work function metal, enabling each device type to have optimized threshold voltage characteristics tailored to its specific operational requirements, thus resolving the contradiction between power efficiency optimization and structural simplicity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent systematically varies the work function parameter across different FET devices by selecting appropriate metals. This parameter change enables independent optimization of threshold voltages for nFETs and pFETs, allowing the circuit to achieve optimal switching delay and power efficiency characteristics that would be impossible with a uniform threshold voltage approach.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If gate-all-around stacked CFET structure with multiple threshold voltages is implemented, then switching delay and power efficiency are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveswitching delayVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the manufacturing process into distinct stages: first forming the gate-all-around structure with high-k dielectric, then selectively depositing different work function metals on nFET and pFET regions, and finally forming source and drain contacts. This segmentation of the complex manufacturing process into manageable sequential steps makes the advanced structure more manufacturable while preserving the performance benefits of multiple threshold voltages.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11894436B2Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages
Publication Date: 2024.02.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11894436B2 patent drawing
  • US11894436B2 patent drawing
  • US11894436B2 patent drawing

AI summary

A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. The first CFET includes a top FET and a bottom FET. The top FET and bottom FET of the first CFET include at least one nanosheet channel. A gate affiliated with the first CFET and the second CFET devices includes a continuous horizontal dielectric over the entire length of the gate. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.