Stacked CFET Conductive Trace Layout for Internal Routability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the semiconductor industry, three-dimensional designs such as complementary field-effect transistors (CFETs) face challenges in internal routability and area utility due to complex configurations of conductive structures and gate arrangements, which affect the efficiency and density of integrated circuits.
Innovation Solution
The implementation of a conductive trace that couples components in a CFET structure, interposed between and overlapping active areas and conductive segments, allows for improved internal routability and area utilization by connecting conductive segments and gates in a stacked transistor configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar FET designs are used, then fabrication and design are simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar two-dimensional FET designs to three-dimensional stacked CFET architectures, utilizing the vertical dimension to increase device density. Multiple transistor layers are stacked vertically with conductive traces routing signals between layers, enabling higher productivity without proportionally increasing footprint area.
2Adaptability or versatility
If multiple conductive structures are added to couple CFET components, then device functionality is improved, but internal routability becomes more difficult
Solution Approach 1:
The patent divides the conductive routing function into separate segments: conductive traces for horizontal routing within layers and vertical interconnects for coupling between layers. This segmentation allows independent optimization of routing paths and simplifies the complexity of interconnecting multiple CFET components while maintaining versatility.
3Area of stationary object
If conductive traces are placed between active areas, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces conductive traces as intermediary elements that bridge active areas and conductive segments without requiring direct contact between critical components. These traces provide routing flexibility and buffer manufacturing tolerances, improving area utilization while reducing the stringency of precision requirements for direct component alignment.
Data Source
AI summary
A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace. The first transistor includes first conductive segments, corresponding to drain and source terminals of the first transistor and extending in a first direction, on a first layer. The second transistor includes second conductive segments, corresponding to drain and source terminals of the second transistor and extending in the first direction, on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in the first direction, and the third layer is interposed between the first and second layers. The first conductive segments, the second conductive segments, and the conductive trace overlap in a layout view.