Stacked CFET Source/Drain Contacts With Wrap-Around Isolation
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Solution Overview
Problem
Current technologies face challenges in scaling complementary field effect transistors (CFETs) beyond 5 nm due to complexities in independently growing nFET and pFET source/drain epitaxy while maintaining vertical integration and electrical disconnection, and optimizing source/drain contact resistance, especially in forming wrap-around contacts for shared source/drain regions.
Innovation Solution
The implementation of CFET structures with wrap-around contacts for shared source/drain regions and independent non-wrap-around contacts for respective nFET/pFET source/drain regions, which provides low contact resistance and maintains electrical separation, utilizing a method that involves epitaxial growth and sacrificial material merging to form shared contacts and encapsulating with dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wrap-around contacts are formed for shared source/drain regions, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the source/drain contact formation into two distinct types: wrap-around contacts for shared source/drain regions and independent contacts for individual transistor source/drain regions. This segmentation allows each contact type to be optimized independently, reducing overall contact resistance while managing manufacturing complexity through differentiated processing steps.
Solution Approach 2:
The patent merges the source/drain regions of stacked transistors to share common contacts, reducing the total number of contacts required. By combining multiple source/drain regions into shared regions, the patent achieves lower contact resistance with fewer contact structures, thereby reducing manufacturing complexity despite the sophisticated wrap-around geometry.
2Device complexity
If source/drain regions are merged to form shared contacts, then the number of contacts is reduced, but electrical separation between transistors becomes more difficult
Solution Approach 1:
The patent applies local quality by using different dielectric materials in different regions: a first dielectric material is disposed in contact with shared source/drain regions to provide electrical isolation, while a second dielectric material is used for independent contacts. This localized differentiation ensures proper electrical separation is maintained at critical interfaces while allowing shared contacts elsewhere, reducing the total number of contacts without compromising isolation.
3Manufacturing precision
If epitaxial growth is used to grow source/drain regions, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent employs preliminary action by using epitaxial growth to pre-form the source/drain regions with precise dimensional control and material composition before subsequent contact formation steps. This preliminary epitaxial formation establishes the foundation for both shared and independent contacts, ensuring manufacturing precision is achieved early in the process while subsequent steps build upon this precisely formed structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low contact resistance and effective electrical separation in aggressively scaled architectures, enhancing the scalability and performance of CFETs by increasing the contact area and preserving the aggressively scaled contacted poly pitch.
Implementation Method 1
a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain region and further in contact with a vertical surface and top surface of the second source/drain region
Implementation Method 2
a second dielectric material disposed as an interlayer dielectric material encapsulating the first and second transistors
Data Source
AI summary
A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the first source/drain region comprises a smaller cross-section than the second source/drain region, a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain region and further in contact with a vertical surface and top surface of the second source/drain region, and a second dielectric material disposed as an interlayer dielectric material encapsulating the first and second transistors.