Stacked Channel Semiconductor Structure With Arch Support Pattern
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Solution Overview
Problem
The reduction in size of MOS-FETs leads to deterioration in operational characteristics of semiconductor devices, necessitating improved electric characteristics for high-performance semiconductor devices.
Innovation Solution
A semiconductor device design featuring a substrate with first and second regions, each containing active patterns and channel patterns, connected by a supporting pattern with an arch-shaped section, and gate electrodes on these channel patterns, along with specific materials and insulating layers to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MOS-FETs are scaled down to reduce size, then device dimensions are reduced, but operational characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns, allowing multiple channels to occupy the same footprint area. This dimensional change enables continued scaling of device density while maintaining effective channel length and operational characteristics through vertical stacking rather than horizontal compression.
Solution Approach 2:
The channel pattern is divided into multiple discrete semiconductor patterns stacked vertically, with each stack forming an independent channel. This segmentation allows each channel to maintain optimal dimensions for operational characteristics while multiple channels collectively provide the required device density and performance.
2Length of moving object
If channel patterns are made shorter to reduce device length, then device size is reduced, but electrical performance deteriorates
Solution Approach 1:
The patent extends the channel dimension vertically into the third dimension, creating stacked channels that provide sufficient effective channel length for electrical performance while keeping the horizontal footprint compact. Multiple vertical channels contribute additively to overall device performance.
Solution Approach 2:
The patent employs composite material structures including alternating semiconductor layers and sacrificial layers with different materials properties. This composite approach enables precise control of channel characteristics and electrical performance through material selection and layer composition.
3Reliability
If multiple semiconductor patterns are stacked to increase channel length, then electrical performance is improved, but structural stability deteriorates
Solution Approach 1:
The patent introduces sacrificial layers as intermediary structures between semiconductor patterns during fabrication. These sacrificial layers provide structural support and spacing during the stacking process, enabling precise formation of multi-layer channels. After fabrication, the sacrificial layers are removed to create the final channel structure.
Solution Approach 2:
The patent employs support structures and sacrificial layers beforehand to maintain structural integrity during the complex stacking and fabrication processes. These preliminary structural elements prevent collapse or misalignment of stacked patterns, ensuring structural stability is maintained throughout manufacturing.
Data Source
AI summary
A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.