Vertically Stacked Channel Semiconductor Device With Composite Spacers
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to high integration, necessitating improved methods for fabricating devices with superior performance and reliability.
Innovation Solution
A semiconductor device design featuring vertically stacked channel layers, a gate electrode surrounding these layers, and a gate spacer composed of alternately stacked first and second spacer patterns, which enhances electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar channel structures to vertically stacked channel layers (multi-layer channel structure), moving the channel conduction path into the vertical dimension. This allows multiple channels to be stacked above each other, increasing device density while maintaining effective gate control over each channel layer, thus improving integration without sacrificing operating characteristics.
Solution Approach 2:
The gate electrode completely surrounds each channel layer in a wrap-around configuration, with the gate wrapping around the channel from front, back, and sidewalls. This nested arrangement provides all-around gate control over the channel, ensuring effective electrostatic control and carrier modulation even in the scaled-down vertical channel structure, thereby maintaining reliability at higher integration densities.
2Loss of energy
If gate spacers are made thinner to reduce capacitance, then leakage currents increase, but if made thicker, then capacitance increases
Solution Approach 1:
The gate spacer is constructed as a composite structure with multiple layers having different material compositions and properties. The first gate spacer layer and second gate spacer layer use different materials with complementary characteristics, allowing the structure to simultaneously achieve low capacitance (through thin overall thickness) and low leakage current (through material properties that block carrier tunneling), thus resolving the trade-off between these two parameters.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.